Kris Gaj
Orcid: 0000-0002-5050-8748Affiliations:
- George Mason University, Fairfax VA, USA
According to our database1,
Kris Gaj
authored at least 137 papers
between 1997 and 2023.
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Bibliography
2023
Engineering Practical Rank-Code-Based Cryptographic Schemes on Embedded Hardware. A Case Study on ROLLO.
IEEE Trans. Computers, July, 2023
High-Speed Hardware Architectures and FPGA Benchmarking of CRYSTALS-Kyber, NTRU, and Saber.
IEEE Trans. Computers, February, 2023
SCA Evaluation and Benchmarking of Finalists in the NIST Lightweight Cryptography Standardization Process.
IACR Cryptol. ePrint Arch., 2023
Proceedings of the Post-Quantum Cryptography - 14th International Workshop, 2023
Proceedings of the Progress in Cryptology - AFRICACRYPT 2023, 2023
2022
IACR Cryptol. ePrint Arch., 2022
IACR Cryptol. ePrint Arch., 2022
CRC-Oriented Error Detection Architectures of Post-quantum Cryptography Niederreiter Key Generator on FPGA.
Proceedings of the IEEE Nordic Circuits and Systems Conference, NorCAS 2022, Oslo, 2022
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022
2021
IACR Cryptol. ePrint Arch., 2021
IACR Cryptol. ePrint Arch., 2021
IACR Cryptol. ePrint Arch., 2021
Fast NEON-Based Multiplication for Lattice-Based NIST Post-quantum Cryptography Finalists.
Proceedings of the Post-Quantum Cryptography - 12th International Workshop, 2021
Side-channel Resistant Implementations of a Novel Lightweight Authenticated Cipher with Application to Hardware Security.
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021
Hardware Benchmarking of Round 2 Candidates in the NIST Lightweight Cryptography Standardization Process.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
2020
FPGA Benchmarking of Round 2 Candidates in the NIST Lightweight Cryptography Standardization Process: Methodology, Metrics, Tools, and Results.
IACR Cryptol. ePrint Arch., 2020
Implementation and Benchmarking of Round 2 Candidates in the NIST Post-Quantum Cryptography Standardization Process Using Hardware and Software/Hardware Co-design Approaches.
IACR Cryptol. ePrint Arch., 2020
Special Session: The Recent Advance in Hardware Implementation of Post-Quantum Cryptography.
Proceedings of the 38th IEEE VLSI Test Symposium, 2020
Sampling from Discrete Distributions in Combinational Hardware with Application to Post-Quantum Cryptography.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Lightweight Implementation of the LowMC Block Cipher Protected Against Side-Channel Attacks.
Proceedings of the 4th ACM Workshop on Attacks and Solutions in Hardware Security Workshop, 2020
High-Level Synthesis in Implementing and Benchmarking Number Theoretic Transform in Lattice-Based Post-Quantum Cryptography Using Software/Hardware Codesign.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2020
2019
A Comprehensive Framework for Fair and Efficient Benchmarking of Hardware Implementations of Lightweight Cryptography.
IACR Cryptol. ePrint Arch., 2019
IACR Cryptol. ePrint Arch., 2019
IACR Cryptol. ePrint Arch., 2019
Full hardware implementation of the Post-Quantum Public-Key Cryptography Scheme Round5.
Proceedings of the 2019 International Conference on ReConFigurable Computing and FPGAs, 2019
Proceedings of the 22nd International Symposium on Research in Attacks, 2019
Evaluating the Potential for Hardware Acceleration of Four NTRU-Based Key Encapsulation Mechanisms Using Software/Hardware Codesign.
Proceedings of the Post-Quantum Cryptography - 10th International Conference, 2019
An Automated Scheduler-Based Approach for the Development of Cryptoprocessors for Pairing-Based Cryptosystems.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium Workshops, 2019
A High-Level Synthesis Approach to the Software/Hardware Codesign of NTT-Based Post-Quantum Cryptography Algorithms.
Proceedings of the International Conference on Field-Programmable Technology, 2019
Implementing and Benchmarking Three Lattice-Based Post-Quantum Cryptography Algorithms Using Software/Hardware Codesign.
Proceedings of the International Conference on Field-Programmable Technology, 2019
Software/Hardware Codesign of the Post Quantum Cryptography Algorithm NTRUEncrypt Using High-Level Synthesis and Register-Transfer Level Design Methodologies.
Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019
2018
IACR Cryptol. ePrint Arch., 2018
Comparison of Cost of Protection against Differential Power Analysis of Selected Authenticated Ciphers.
Cryptogr., 2018
Comparing the Cost of Protecting Selected Lightweight Block Ciphers against Differential Power Analysis in Low-Cost FPGAs.
Comput., 2018
Proceedings of the 2018 International Conference on ReConFigurable Computing and FPGAs, 2018
LUT-Lock: A Novel LUT-Based Logic Obfuscation for FPGA-Bitstream and ASIC-Hardware Protection.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018
Benchmarking the Capabilities and Limitations of SAT Solvers in Defeating Obfuscation Schemes.
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018
Challenges and Rewards of Implementing and Benchmarking Post-Quantum Cryptography in Hardware.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018
Proceedings of the International Conference on Field-Programmable Technology, 2018
Proceedings of the 2018 Workshop on Attacks and Solutions in Hardware Security, 2018
2017
Microprocess. Microsystems, 2017
Microprocess. Microsystems, 2017
RTL implementations and FPGA benchmarking of selected CAESAR Round Two authenticated ciphers.
Microprocess. Microsystems, 2017
Area-oriented comparison of lightweight block ciphers implemented in hardware for the activation mechanism in the anti-counterfeiting schemes.
Int. J. Circuit Theory Appl., 2017
A scalable ECC processor implementation for high-speed and lightweight with side-channel countermeasures.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2017
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2017
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2017
A Generic Approach to the Development of Coprocessors for Elliptic Curve Cryptosystems.
Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium Workshops, 2017
Proceedings of the International Conference on Field Programmable Technology, 2017
Toward a new HLS-based methodology for FPGA benchmarking of candidates in cryptographic competitions: The CAESAR contest case study.
Proceedings of the International Conference on Field Programmable Technology, 2017
Comparison of hardware and software implementations of selected lightweight block ciphers.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017
Analysis and Inner-Round Pipelined Implementation of Selected Parallelizable CAESAR Competition Candidates.
Proceedings of the Euromicro Conference on Digital System Design, 2017
2016
A Zynq-based testbed for the experimental benchmarking of algorithms competing in cryptographic contests.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2016
Proceedings of the Progress in Cryptology - INDOCRYPT 2016, 2016
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016
High-Speed RTL Implementations and FPGA Benchmarking of Three Authenticated Ciphers Competing in CAESAR Round Two.
Proceedings of the 24th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2016
Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016
RTL Implementations and FPGA Benchmarking of Three Authenticated Ciphers Competing in CAESAR Round Two.
Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016
Proceedings of the 53rd Annual Design Automation Conference, 2016
2015
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015
Hardware Benchmarking of Cryptographic Algorithms Using High-Level Synthesis Tools: The SHA-3 Contest Case Study.
Proceedings of the Applied Reconfigurable Computing - 11th International Symposium, 2015
Proceedings of the Applied Reconfigurable Computing - 11th International Symposium, 2015
Proceedings of the 10th International Conference on Availability, Reliability and Security, 2015
2014
IACR Cryptol. ePrint Arch., 2014
Can high-level synthesis compete against a hand-written code in the cryptographic domain? A case study.
Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs, 2014
A novel modular adder for one thousand bits and more using fast carry chains of modern FPGAs.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014
2013
A high-speed unified hardware architecture for 128 and 256-bit security levels of AES and the SHA-3 candidate Grøstl.
Microprocess. Microsystems, 2013
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013
2012
Selected Papers from the International Conference on Reconfigurable Computing and FPGAs (ReConFig'10).
Int. J. Reconfigurable Comput., 2012
IACR Cryptol. ePrint Arch., 2012
Comprehensive Evaluation of High-Speed and Medium-Speed Implementations of Five SHA-3 Finalists Using Xilinx and Altera FPGAs.
IACR Cryptol. ePrint Arch., 2012
Option space exploration using distributed computing for efficient benchmarking of FPGA cryptographic modules.
Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012
2011
IEEE Trans. Computers, 2011
Proceedings of the 2011 International Conference on Field-Programmable Technology, 2011
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011
Cryptographic Contests: Toward Fair and Comprehensive Benchmarking of Cryptographic Algorithms in Hardware (Abstract).
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011
Throughput vs. Area Trade-offs in High-Speed Architectures of Five Round 3 SHA-3 Candidates Implemented Using Xilinx and Altera FPGAs.
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2011 - 13th International Workshop, Nara, Japan, September 28, 2011
2010
Area-Time Efficient Implementation of the Elliptic Curve Method of Factoring in Reconfigurable Hardware for Application in the Number Field Sieve.
IEEE Trans. Computers, 2010
IACR Cryptol. ePrint Arch., 2010
ATHENa - Automated Tool for Hardware EvaluatioN: Toward Fair and Comprehensive Benchmarking of Cryptographic Hardware Using FPGAs.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010
Fair and Comprehensive Methodology for Comparing Hardware Performance of Fourteen Round Two SHA-3 Candidates Using FPGAs.
Proceedings of the Cryptographic Hardware and Embedded Systems, 2010
2009
IEEE Trans. Computers, 2009
Proceedings of the Cryptographic Engineering, 2009
2008
Parallel Comput., 2008
FPGA accelerated multipliers over binary composite fields constructed via low hamming weight irreducible polynomials.
IET Comput. Digit. Tech., 2008
Proceedings of the 2008 International Conference on Field-Programmable Technology, 2008
2007
IACR Cryptol. ePrint Arch., 2007
Computer, 2007
2006
System-level parallelism and concurrency maximisation in reconfigurable computing applications.
Int. J. Embed. Syst., 2006
IACR Cryptol. ePrint Arch., 2006
Proceedings of the ACM/IEEE SC2006 Conference on High Performance Networking and Computing, 2006
Proceedings of the Cryptographic Hardware and Embedded Systems, 2006
Proceedings of the Advanced International Conference on Telecommunications and International Conference on Internet and Web Applications and Services (AICT/ICIW 2006), 2006
2005
Analysis of Attacks and Defense Mechanisms for QoS Signaling Protocols in MANETs.
Proceedings of the Wireless Information Systems, 2005
Secure Partial Reconfiguration of FPGAs.
Proceedings of the 2005 IEEE International Conference on Field-Programmable Technology, 2005
Low Latency Elliptic Curve Cryptography Accelerators for NIST Curves Over Binary Fields.
Proceedings of the 2005 IEEE International Conference on Field-Programmable Technology, 2005
Implementation of EAX Mode of Operation for FPGA Bitstream Encryption and Authentication.
Proceedings of the 2005 IEEE International Conference on Field-Programmable Technology, 2005
A System-Level Design Methodology for Reconfigurable Computing Applications.
Proceedings of the 2005 IEEE International Conference on Field-Programmable Technology, 2005
High-Throughput Reconfigurable Computing: A Design Study of an IDEA Encryption Cryptosystem on the SRC-6e Reconfigurable Computer.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005
Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, 2005
Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, 2005
2004
System-Level Parallelism and Throughput Optimization in Designing Reconfigurable Computing Applications.
Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004
Wavelet spectral dimension reduction of hyperspectral imagery on a reconfigurable computer.
Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology, 2004
Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology, 2004
Reconfigurable hardware implementation of mesh routing in number field sieve factorization.
Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology, 2004
Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, 2004
Implementation of elliptic curve cryptosystems over GF(2<sup>n</sup>) in optimal normal basis on a reconfigurable computer.
Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, 2004
Distributed CA-based PKI for Mobile Ad Hoc Networks Using Elliptic Curve Cryptography.
Proceedings of the Public Key Infrastructure, 2004
Proceedings of the Topics in Cryptology, 2004
Efficient Linear Array for Multiplication in GF(2<sup>m</sup>) Using a Normal Basis for Elliptic Curve Cryptography.
Proceedings of the Cryptographic Hardware and Embedded Systems, 2004
Proceedings of the Content Computing, Advanced Workshop on Content Computing, 2004
2003
Effective Utilization and Reconfiguration of Distributed Hardware Resources Using Job Management Systems.
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003
Proceedings of the 2003 IEEE International Conference on Field-Programmable Technology, 2003
Exploiting system-level parallelism in the application development on a reconfigurable computer.
Proceedings of the 2003 IEEE International Conference on Field-Programmable Technology, 2003
An Implementation Comparison of an IDEA Encryption Cryptosystem on Two General-Purpose Reconfigurable Computers.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003
Proceedings of the Advances in Cryptology, 2003
Proceedings of the Cryptographic Hardware and Embedded Systems, 2003
2002
Comparative Analysis of the Hardware Implementations of Hash Functions SHA-1 and SHA-512.
Proceedings of the Information Security, 5th International Conference, 2002
Proceedings of the 16th International Parallel and Distributed Processing Symposium (IPDPS 2002), 2002
2001
Experimental Testing of the Gigabit IPSec-Compliant Implementations of Rijndael and Triple DES Using SLAAC-1V FPGA Accelerator Board.
Proceedings of the Information Security, 4th International Conference, 2001
Fast implementations of secret-key block ciphers using mixed inner- and outer-round pipelining.
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2001
Fast Implementation and Fair Comparison of the Final Candidates for Advanced Encryption Standard Using Field Programmable Gate Arrays.
Proceedings of the Topics in Cryptology, 2001
2000
Comparison of the Hardware Performance of the AES Candidates Using Reconfigurable Hardware.
Proceedings of the Third Advanced Encryption Standard Candidate Conference, 2000
1997
J. VLSI Signal Process., 1997