Brad L. Hutchings

Orcid: 0000-0002-2991-0230

Affiliations:
  • Brigham Young University, Provo, Utah, USA


According to our database1, Brad L. Hutchings authored at least 77 papers between 1989 and 2023.

Collaborative distances:

Awards

IEEE Fellow

IEEE Fellow 2018, "For contributions to CAD tools for reconfigurable computing".

Timeline

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Bibliography

2023
Improving the Reliability of FPGA CRO PUFs.
Proceedings of the 33rd International Conference on Field-Programmable Logic and Applications, 2023

2022
Inducing Non-uniform FPGA Aging Using Configuration-based Short Circuits.
ACM Trans. Reconfigurable Technol. Syst., 2022

Approaches for FPGA Design Assurance.
ACM Trans. Reconfigurable Technol. Syst., 2022

Cloning the Unclonable: Physically Cloning an FPGA Ring-Oscillator PUF.
Proceedings of the International Conference on Field-Programmable Technology, 2022

2020
Using Novel Configuration Techniques for Accelerated FPGA Aging.
Proceedings of the 30th International Conference on Field-Programmable Logic and Applications, 2020

2019
Preallocating Resources for Distributed Memory Based FPGA Debug.
Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

2018
Enhancing debug observability for HLS-based FPGA circuits through source-to-source compilation.
J. Parallel Distributed Comput., 2018

Using Physical and Functional Comparisons to Assure 3rd-Party IP for Modern FPGAs.
Proceedings of the 3rd IEEE International Verification and Security Workshop, 2018

Distributed-Memory Based FPGA Debug: Design Timing Impact.
Proceedings of the International Conference on Field-Programmable Technology, 2018

Enabling Low Impact, Rapid Debug for Highly Utilized FPGA Designs.
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

Demand Driven Assembly of FPGA Configurations Using Partial Reconfiguration, Ubuntu Linux, and PYNQ.
Proceedings of the 26th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2018

2017
Rapid implementation of a partially reconfigurable video system with PYNQ.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

2016
Packing a modern Xilinx FPGA using RapidSmith.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2016

2015
Using shadow pointers to trace C pointer values in FPGA circuits.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

Using source-to-source compilation to instrument circuits for debug with High Level Synthesis.
Proceedings of the 2015 International Conference on Field Programmable Technology, 2015

Using Source-Level Transformations to Improve High-Level Synthesis Debug and Validation on FPGAs.
Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015

RapidSmith 2: A Framework for BEL-level CAD Exploration on Xilinx FPGAs.
Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015

2014
New approaches for in-system debug of behaviorally-synthesized FPGA circuits.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

A power side-channel-based digital to analog converterfor Xilinx FPGAs.
Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014

Rapid Post-Map Insertion of Embedded Logic Analyzers for Xilinx FPGAs.
Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014

2013
Optimization techniques for a high level synthesis implementation of the Sobel filter.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013

Improving clock-rate of hard-macro designs.
Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

Impact of hard macro size on FPGA clock rate and place/route time.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

Implementing high-performance, low-power FPGA-based optical flow accelerators in C.
Proceedings of the 24th International Conference on Application-Specific Systems, 2013

2012
The NII Shonan Configurable Computing Workshop (NII Shonan Meeting 2012-11).
NII Shonan Meet. Rep., 2012

A Fault Injection Analysis of Linux Operating on an FPGA-Embedded Platform.
Int. J. Reconfigurable Comput., 2012

Profiling FPGA floor-planning effects on timing closure.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

2011
RapidSmith: Do-It-Yourself CAD Tools for Xilinx FPGAs.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

FPGA Communication Framework.
Proceedings of the IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines, 2011

HMFlow: Accelerating FPGA Compilation with Hard Macros for Rapid Prototyping.
Proceedings of the IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines, 2011

2010
Fault Injection Results of Linux Operating on an FPGA Embedded Platform.
Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010

Rapid prototyping tools for FPGA designs: RapidSmith.
Proceedings of the International Conference on Field-Programmable Technology, 2010

Using Hard Macros to Reduce FPGA Compilation Time.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

2009
Comparing fine-grained performance on the Ambric MPPA against an FPGA.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

Optical Flow on the Ambric Massively Parallel Processor Array (MPPA).
Proceedings of the FCCM 2009, 2009

2008
Design, Debug, Deploy: The Creation of Configurable Computing Applications.
J. Signal Process. Syst., 2008

Design Productivity for Configurable Computing.
Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2008

2004
GigaOp DSP on FPGA.
J. VLSI Signal Process., 2004

What is the right model for programming and using modern FPGAs?
Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, 2004

2003
Reconfigurable Computing Application Frameworks.
Proceedings of the 11th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2003), 2003

Simulation and Synthesis of CSP-based Interprocess Communication.
Proceedings of the 11th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2003), 2003

Source Level Debugger for the Sea Cucumber Synthesizing Compiler.
Proceedings of the 11th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2003), 2003

Adaptive computing: what can it do, where can it go?
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

Issues in debugging highly parallel FPGA-based applications derived from source code.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002
Algorithms for Coloring Quadtrees.
Algorithmica, 2002

Sea Cucumber: A Synthesizing Compiler for FPGAs.
Proceedings of the Field-Programmable Logic and Applications, 2002

Multitasking Hardware on the SLAAC1-V Reconfigurable Computing System.
Proceedings of the Field-Programmable Logic and Applications, 2002

Assisting Network Intrusion Detection with Reconfigurable Hardware.
Proceedings of the 10th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2002), 2002

2001
Designing Run-Time Reconfigurable Systems with JHDL.
J. VLSI Signal Process., 2001

Unifying simulation and execution in a design environment for FPGA systems.
IEEE Trans. Very Large Scale Integr. Syst., 2001

Synthesizing RTL Hardware from Java Byte Codes.
Proceedings of the Field-Programmable Logic and Applications, 2001

Using Design-Level Scan to Improve FPGA Design Observability and Controllability for Functional Verification.
Proceedings of the Field-Programmable Logic and Applications, 2001

An Application-Specific Compiler for High-Speed Binary Image Morphology.
Proceedings of the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2001

Instrumenting Bitstreams for Debugging FPGA Circuits.
Proceedings of the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2001

2000
Designing and Debugging Custom Computing Applications.
IEEE Des. Test Comput., 2000

Improving the FPGA Design Process through Determining and Applying Logical-to-Physical Design Mappings.
Proceedings of the 8th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2000), 2000

Using general-purpose programming languages for FPGA design.
Proceedings of the 37th Conference on Design Automation, 2000

1999
A Reconfigurable Arithmetic Array for Multimedia Application.
Proceedings of the 1999 ACM/SIGDA Seventh International Symposium on Field Programmable Gate Arrays, 1999

A CAD Suite for High-Performance FPGA Design.
Proceedings of the 7th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '99), 1999

1998
Improving functional density using run-time circuit reconfiguration [FPGAs].
IEEE Trans. Very Large Scale Integr. Syst., 1998

The flexibility of configurable computing.
IEEE Signal Process. Mag., 1998

JHDL - An HDL for Reconfigurable Systems.
Proceedings of the 6th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '98), 1998

1997
ASICs, Processors, and Configurable Computing.
Proceedings of the 30th Annual Hawaii International Conference on System Sciences (HICSS-30), 1997

Exploiting reconfigurability through domain-specific systems.
Proceedings of the Field-Programmable Logic and Applications, 7th International Workshop, 1997

Improving Functional Density Through Run-Time Constant Propagation.
Proceedings of the 1997 ACM/SIGDA Fifth International Symposium on Field Programmable Gate Arrays, 1997

Automated target recognition on SPLASH 2.
Proceedings of the 5th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '97), 1997

1996
Run-Time Reconfiguration: A method for enhancing the functional density of SRAM-based FPGAs.
J. VLSI Signal Process., 1996

Sequencing Run-Time Reconfigured Hardware with Software.
Proceedings of the 1996 Fourth International Symposium on Field Programmable Gate Arrays, 1996

Supporting FPGA microprocessors through retargetable software tools.
Proceedings of the 4th IEEE Symposium on FPGAs for Custom Computing Machines (FCCM '96), 1996

Mixing fixed and reconfigurable logic for array processing.
Proceedings of the 4th IEEE Symposium on FPGAs for Custom Computing Machines (FCCM '96), 1996

1995
An Assessment of the Suitability of FPGA-Based Systems for Use in Digital Signal Processing.
Proceedings of the Field-Programmable Logic and Applications, 5th International Workshop, 1995

Implementation Approaches for Reconfigurable Logic Applications.
Proceedings of the Field-Programmable Logic and Applications, 5th International Workshop, 1995

A dynamic instruction set computer.
Proceedings of the 3rd IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '95), 1995

Design methodologies for partially reconfigured systems.
Proceedings of the 3rd IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '95), 1995

1994
Multiple-Layer Cross-Field Ultrasonic Tactile Sensor.
Proceedings of the 1994 International Conference on Robotics and Automation, 1994

High-Speed Circuit Design: CAD Tools and Computational Challenges.
Proceedings of the 27th Annual Hawaii International Conference on System Sciences (HICSS-27), 1994

1989
VLSI design and implementation of a real-time image segmentation processor.
Mach. Vis. Appl., 1989


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