Peter C. S. Scholtens

According to our database1, Peter C. S. Scholtens authored at least 4 papers between 2002 and 2005.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2005
Systematic power reduction and performance analysis of mismatch limited ADC designs.
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

2004
Assessment of the merits of CMOS technology scaling for analog circuit design.
Proceedings of the 33rd European Solid-State Circuits Conference, 2004

A 1.6 GS/s, 16 times interleaved track & hold with 7.6 ENOB in 0.12 μm CMOS [ADC applications].
Proceedings of the 33rd European Solid-State Circuits Conference, 2004

2002
A 6-b 1.6-Gsample/s flash ADC in 0.18-μm CMOS using averaging termination.
IEEE J. Solid State Circuits, 2002


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