Ed van Tuijl

According to our database1, Ed van Tuijl authored at least 18 papers between 2004 and 2017.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2017
An energy reduced sampling technique applied to a 10b 1MS/s SAR ADC.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017

Range pre-selection sampling technique to reduce input drive energy for SAR ADCs.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017

2015
15.3 A 115dB-DR audio DAC with -61dBFS out-of-band noise.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

Session 5 overview: Analog techniques: Analog subcommittee.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2014
Towards minimum achievable phase noise of relaxation oscillators.
Int. J. Circuit Theory Appl., 2014

2011
A narrow-to-wideband scrambling technique increasing software radio receiver linearity.
Proceedings of the 37th European Solid-State Circuits Conference, 2011

2010
Power Efficient Gigabit Communication Over Capacitively Driven RC-Limited On-Chip Interconnects.
IEEE J. Solid State Circuits, 2010

A 10-bit Charge-Redistribution ADC Consuming 1.9 μ W at 1 MS/s.
IEEE J. Solid State Circuits, 2010

2009
Low-Power, High-Speed Transceivers for Network-on-Chip Communication.
IEEE Trans. Very Large Scale Integr. Syst., 2009

2008
A 90μW 12MHz Relaxation Oscillator with a -162dB FOM.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

A 1.9μW 4.4fJ/Conversion-step 10b 1MS/s Charge-Redistribution ADC.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

Audio at low and high power.
Proceedings of the ESSCIRC 2008, 2008

Session 20 - Advanced wireline techniques.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2007
Optimal Positions of Twists in Global On-Chip Differential Interconnects.
IEEE Trans. Very Large Scale Integr. Syst., 2007

A Double-Tail Latch-Type Voltage Sense Amplifier with 18ps Setup+Hold Time.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

A 0.28pJ/b 2Gb/s/ch Transceiver in 90nm CMOS for 10mm On-Chip interconnects.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

A Time-Interleaved Track & hold in 0.13 μm CMOS sub-sampling a 4 GHz signal with 43 dB SNDR.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2004
Reducing quantization noise with recursive Sigma Delta modulators.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004


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