Peter Caputa

According to our database1, Peter Caputa authored at least 6 papers between 2004 and 2011.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
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Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2011

2006
A 3Gb/s/wire Global On-Chip Bus with Near Velocity-of-Light Latency.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

An on-chip delay- and skew-insensitive multicycle communication scheme.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2005
Well-behaved global on-chip interconnect.
IEEE Trans. Circuits Syst. I Regul. Pap., 2005

2004
An Extended Transition Energy Cost Model for Buses in Deep Submicron Technologies.
Proceedings of the Integrated Circuit and System Design, 2004

A low-swing single-ended L1 cache bus technique for sub-90nm technologies.
Proceedings of the 33rd European Solid-State Circuits Conference, 2004


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