Ram Krishnamurthy
Orcid: 0000-0002-2428-7099Affiliations:
- Intel Corporation, Circuit Research Lab, Hillsboro, OR, USA
- Carnegie Mellon University, Pittsburgh, PA, USA (PhD 1997)
- State University of New York at Buffalo, Center of Excellence for Document Analysis and Recognition, NY, USA
According to our database1,
Ram Krishnamurthy
authored at least 138 papers
between 1995 and 2024.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 2011, "For contributions to high performance and low power digital circuits for microprocessors".
Timeline
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Online presence:
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on linkedin.com
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on intel.com
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On csauthors.net:
Bibliography
2024
DIMCA: An Area-Efficient Digital In-Memory Computing Macro Featuring Approximate Arithmetic Hardware in 28 nm.
IEEE J. Solid State Circuits, March, 2024
2023
IEEE J. Solid State Circuits, 2023
microASR: 32-μW Real-Time Automatic Speech Recognition Chip featuring a Bio-Inspired Neuron Model and Digital SRAM-based Compute-In-Memory Hardware.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023
93.89% Peak Efficiency 24V-to-1V DC-DC Converter with Fast In-Situ Efficiency Tracking and Power-FET Code Roaming.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023
2022
An Inductor-First Single-Inductor Multiple-Output Hybrid DC-DC Converter With Integrated Flying Capacitor for SoC Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
2.4GHz, Double-Buffered, 4kb Standard-Cell-Based Register File with Low-Power Mixed-Frequency Clocking for Machine Learning Accelerators.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
DIMC: 2219TOPS/W 2569F2/b Digital In-Memory Computing Macro in 28nm Based on Approximate Arithmetic Hardware.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022
2021
IEEE Trans. Very Large Scale Integr. Syst., 2021
IEEE J. Solid State Circuits, 2021
2020
A 4900- $\mu$ m<sup>2</sup> 839-Mb/s Side-Channel Attack- Resistant AES-128 in 14-nm CMOS With Heterogeneous Sboxes, Linear Masked MixColumns, and Dual-Rail Key Addition.
IEEE J. Solid State Circuits, 2020
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
A Ray-Casting Accelerator in 10nm CMOS for Efficient 3D Scene Reconstruction in Edge Robotics and Augmented Reality Applications.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
Low-Clock-Power Digital Standard Cell IPs for High-Performance Graphics/AI Processors in 10nm CMOS.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
25.9 Reconfigurable Transient Current-Mode Global Interconnect Circuits in 10nm CMOS for High-Performance Processors with Wide Voltage-Frequency Operating Range.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
25.7 Time-Borrowing Fast Mux-D Scan Flip-Flop with On-Chip Timing/Power/VMIN Characterization Circuits in 10nm CMOS.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
2019
An All-Digital Unified Physically Unclonable Function and True Random Number Generator Featuring Self-Calibrating Hierarchical Von Neumann Extraction in 14-nm Tri-gate CMOS.
IEEE J. Solid State Circuits, 2019
A 4096-Neuron 1M-Synapse 3.8-pJ/SOP Spiking Neural Network With On-Chip STDP Learning and Sparse Weights in 10-nm FinFET CMOS.
IEEE J. Solid State Circuits, 2019
A 250Mv, 0.063J/Ghash Bitcoin Mining Engine in 14nm CMOS Featuring Dual-Vcc Sha256 Datapath and 3-Phase Latch Based Clocking.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
A 1.4GHz 20.5Gbps GZIP decompression accelerator in 14nm CMOS featuring dual-path out-of-order speculative Huffman decoder and multi-write enabled register file array.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
A 4900×m<sup>2</sup> 839Mbps Side-Channel Attack Resistant AES-128 in 14nm CMOS with Heterogeneous Sboxes, Linear Masked MixColumns and Dual-Rail Key Addition.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
A Microwatt-Class Always-On Sensor Fusion Engine Featuring Ultra-Low-Power AOI Clocked Circuits in 14nm CMOS.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
Wednesday Plenary: Machine Learning and Hardware Security Technologies for the Nanoscale era: Challenges & Opportunities.
Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019
Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019
Proceedings of the 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2019
A 225-950mV 1.5Tbps/W Whirlpool Hashing Accelerator for Secure Automotive Platforms in 14nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019
A 220-900mV 179Mcode/s 36pJ/code Canonical Huffman Encoder for DEFLATE Compression in 14nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019
A 54% Power-Saving Static Fully-Interruptible Single-Phase-Clocked Shared-Keeper Flip-Flop in 14nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019
Optimized Fused Floating-Point Many-Term Dot-Product Hardware for Machine Learning Accelerators.
Proceedings of the 26th IEEE Symposium on Computer Arithmetic, 2019
2018
220MV-900MV 794/584/754 GBPS/W Reconfigurable GF(2<sup>4</sup>)2 AES/SMS4/Camellia Symmetric-Key Cipher Accelerator in 14NM Tri-Gate CMOS.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
An All-Digital Unified Static/Dynamic Entropy Generator Featuring Self-Calibrating Hierarchical Von Neumann Extraction for Secure Privacy-Preserving Mutual Authentication in IoT Mote Platforms.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
A 4096-Neuron 1M-Synapse 3.8PJ/SOP Spiking Neural Network with On-Chip STDP Learning and Sparse Weights in 10NM FinFET CMOS.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
2.9TOPS/W Reconfigurable Dense/Sparse Matrix-Multiply Accelerator with Unified INT8/INTI6/FP16 Datapath in 14NM Tri-Gate CMOS.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
A 230mV-950mV 2.8Tbps/W Unified SHA256/SM3 Secure Hashing Hardware Accelerator in 14nm Tri-Gate CMOS.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
A 280mV 3.1pJ/code Huffman Decoder for DEFLATE Decompression Featuring Opportunistic Code Skip and 3-way Symbol Generation in 14nm Tri-gate CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018
Ultra-Lightweight 548-1080 Gate 166Gbps/W-12.6Tbps/W SIMON 32/64 Cipher Accelerators for IoT in 14nm Tri-gate CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018
2017
A 4-fJ/b Delay-Hardened Physically Unclonable Function Circuit With Selective Bit Destabilization in 14-nm Trigate CMOS.
IEEE J. Solid State Circuits, 2017
IEEE Des. Test, 2017
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017
Energy efficient and ultra low voltage security circuits for nanoscale CMOS technologies.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017
Algorithm and hardware design of discrete-time spiking neural networks based on back propagation with binary activations.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017
2016
µRNG: A 300-950 mV, 323 Gbps/W All-Digital Full-Entropy True Random Number Generator in 14 nm FinFET CMOS.
IEEE J. Solid State Circuits, 2016
250mV-950mV 1.1Tbps/W double-affine mapped Sbox based composite-field SMS4 encrypt/decrypt accelerator in 14nm tri-gate CMOS.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016
A 4fJ/bit delay-hardened physically unclonable function circuit with selective bit destabilization in 14nm tri-gate CMOS.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016
A 350mV-900mV 2.1GHz 0.011mm<sup>2</sup> regular expression matching accelerator with aging-tolerant low-VMIN circuits in 14nm tri-gate CMOS.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016
14.4 A 21.5M-query-vectors/s 3.37nJ/vector reconfigurable k-nearest-neighbor accelerator with adaptive precision in 14nm tri-gate CMOS.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
Proceedings of the 34th IEEE International Conference on Computer Design, 2016
A 305mV-850mV 400μW 45GSamples/J reconfigurable compressive sensing engine with early-termination for ultra-low energy target detection in 14nm tri-gate CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016
2015
340 mV-1.1 V, 289 Gbps/W, 2090-Gate NanoAES Hardware Accelerator With Area-Optimized Encrypt/Decrypt GF(2 4 ) 2 Polynomials in 22 nm Tri-Gate CMOS.
IEEE J. Solid State Circuits, 2015
A 340 mV-to-0.9 V 20.2 Tb/s Source-Synchronous Hybrid Packet/Circuit-Switched 16 × 16 Network-on-Chip in 22 nm Tri-Gate CMOS.
IEEE J. Solid State Circuits, 2015
μRNG: A 300-950mV 323Gbps/W all-digital full-entropy true random number generator in 14nm FinFET CMOS.
Proceedings of the ESSCIRC Conference 2015, 2015
2014
340mV-1.1V, 289Gbps/W, 2090-gate NanoAES hardware accelerator with area-optimized encrypt/decrypt GF(2<sup>4</sup>)<sup>2</sup> polynomials in 22nm tri-gate CMOS.
Proceedings of the Symposium on VLSI Circuits, 2014
16.2 A 0.19pJ/b PVT-variation-tolerant hybrid physically unclonable function circuit for 100% stable secure key generation in 22nm CMOS.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
16.1 A 340mV-to-0.9V 20.2Tb/s source-synchronous hybrid packet/circuit-switched 16×16 network-on-chip in 22nm tri-gate CMOS.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
13fJ/bit probing-resilient 250K PUF array with soft darkbit masking for 1.94% bit-error in 22nm tri-gate CMOS.
Proceedings of the ESSCIRC 2014, 2014
2013
A 2.05 GVertices/s 151 mW Lighting Accelerator for 3D Graphics Vertex and Pixel Shading in 32 nm CMOS.
IEEE J. Solid State Circuits, 2013
A 280 mV-to-1.1 V 256b Reconfigurable SIMD Vector Permutation Engine With 2-Dimensional Shuffle in 22 nm Tri-Gate CMOS.
IEEE J. Solid State Circuits, 2013
Proceedings of the 21st IEEE Symposium on Computer Arithmetic, 2013
2012
2.4 Gbps, 7 mW All-Digital PVT-Variation Tolerant True Random Number Generator for 45 nm CMOS High-Performance Microprocessors.
IEEE J. Solid State Circuits, 2012
A 2.8GHz 128-entry × 152b 3-read/2-write multi-precision floating-point register file and shuffler in 32nm CMOS.
Proceedings of the Symposium on VLSI Circuits, 2012
A 2.05GVertices/s 151mW lighting accelerator for 3D graphics vertex and pixel shading in 32nm CMOS.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
A 1.45GHz 52-to-162GFLOPS/W variable-precision floating-point fused multiply-add unit with certainty tracking in 32nm CMOS.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
A 280mV-to-1.1V 256b reconfigurable SIMD vector permutation engine with 2-dimensional shuffle in 22nm CMOS.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
A 260mV 468GOPS/W 256b 4-way to 32-way vector shifter with permute-assisted skip in 22nm tri-gate CMOS.
Proceedings of the 38th European Solid-State Circuit conference, 2012
Proceedings of the 49th Annual Design Automation Conference 2012, 2012
2011
IEEE Trans. Very Large Scale Integr. Syst., 2011
53 Gbps Native GF(2 <sup>4</sup>) <sup>2</sup> Composite-Field AES-Encrypt/Decrypt Accelerator for Content-Protection in 45 nm High-Performance Microprocessors.
IEEE J. Solid State Circuits, 2011
Proceedings of the 37th European Solid-State Circuits Conference, 2011
Proceedings of the 48th Design Automation Conference, 2011
Hybrid Circuit/Packet Switched Network for Energy Efficient on-Chip Interconnections.
Proceedings of the Low Power Networks-on-Chip., 2011
2010
A 300 mV 494GOPS/W Reconfigurable Dual-Supply 4-Way SIMD Vector Processing Accelerator in 45 nm CMOS.
IEEE J. Solid State Circuits, 2010
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
A 4.1Tb/s bisection-bandwidth 560Gb/s/W streaming circuit-switched 8×8 mesh network-on-chip in 45nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
A 320mV-to-1.2V on-die fine-grained reconfigurable fabric for DSP/media accelerators in 32nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
Proceedings of the 36th European Solid-State Circuits Conference, 2010
3GHz, 74mW 2-level Karatsuba 64b Galois field multiplier for public-key encryption acceleration in 45nm CMOS.
Proceedings of the 36th European Solid-State Circuits Conference, 2010
High-Performance Energy-Efficient Reconfigurable Accelerators/Co-processors for Tera-Scale Multi-core Microprocessors.
Proceedings of the Reconfigurable Computing: Architectures, 2010
2009
A 320 mV 56 μW 411 GOPS/Watt Ultra-Low Voltage Motion Estimation Accelerator in 65 nm CMOS.
IEEE J. Solid State Circuits, 2009
Introduction to the Special Issue on the 2008 IEEE International Solid-State Circuits Conference.
IEEE J. Solid State Circuits, 2009
A 4Gbps 0.57pJ/bit Process-Voltage-Temperature Variation Tolerant All-Digital True Random Number Generator in 45nm CMOS.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009
A 300mV 494GOPS/W reconfigurable dual-supply 4-Way SIMD vector processing accelerator in 45nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
2008
Advances in hardware design and implementation of signal processing systems [DSP Forum].
IEEE Signal Process. Mag., 2008
Introduction to the Special Issue on the 2007 IEEE International Solid-State Circuits Conference.
IEEE J. Solid State Circuits, 2008
IEEE J. Solid State Circuits, 2008
A 2.1GHz 6.5mW 64-bit Unified PopCount/BitScan Datapath Unit for 65nm High-Performance Microprocessor Execution Cores.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008
A 320mV 56μW 411GOPS/Watt Ultra-Low Voltage Motion Estimation Accelerator in 65nm CMOS.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
A robust alternate repeater technique for high performance busses in the multi-core era.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Proceedings of the ESSCIRC 2008, 2008
2007
IEEE J. Solid State Circuits, 2007
A 2.4GHz 256/1024-bit Encryption Accelerator reconfigurable Montgomery multiplier in 90nm CMOS.
Proceedings of the 2007 IEEE International SOC Conference, 2007
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
A 200mV to 1.2V, 4.4MHz to 6.3GHz, 48×42b 1R/1W programmable register file in 65nm CMOS.
Proceedings of the 33rd European Solid-State Circuits Conference, 2007
2006
A process variation compensating technique with an on-die leakage current sensor for nanometer scale dynamic circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2006
Introduction to the Special Issue on the 2005 IEEE International Solid-State Circuits Conference.
IEEE J. Solid State Circuits, 2006
IEEE J. Solid State Circuits, 2006
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006
High-performance energy-efficient memory circuit technologies for sub-45nm technologies.
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
2005
IEEE Trans. Very Large Scale Integr. Syst., 2005
Design and analysis of spatial encoding circuits for peak power reduction in on-chip buses.
IEEE Trans. Very Large Scale Integr. Syst., 2005
Designing leakage tolerant, low power wide-OR dominos for sub-130nm CMOS technologies.
Microelectron. J., 2005
IEEE J. Solid State Circuits, 2005
An 8.3GHz dual supply/threshold optimized 32b integer ALU-register file loop in 90nm CMOS.
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005
Proceedings of the 31st European Solid-State Circuits Conference, 2005
Proceedings of the 17th IEEE Symposium on Computer Arithmetic (ARITH-17 2005), 2005
2004
Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004
Leakage Control Techniques for Designing Robust, Low Power Wide-OR Domino Logic for sub-130 nm CMOS Technologies.
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004
Spatial encoding circuit techniques for peak power reduction of on-chip high-performance buses.
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004
Proceedings of the 33rd European Solid-State Circuits Conference, 2004
2003
IEEE J. Solid State Circuits, 2003
A 4.5-GHz 130-nm 32-KB L0 cache with a leakage-tolerant self reverse-bias bitline scheme.
IEEE J. Solid State Circuits, 2003
IEEE J. Solid State Circuits, 2003
Effectiveness and scaling trends of leakage control techniques for sub-130nm CMOS technologies.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003
Proceedings of the ESSCIRC 2003, 2003
Proceedings of the ESSCIRC 2003, 2003
Proceedings of the 16th IEEE Symposium on Computer Arithmetic (Arith-16 2003), 2003
Proceedings of the 16th IEEE Symposium on Computer Arithmetic (Arith-16 2003), 2003
2002
IEEE J. Solid State Circuits, 2002
IEEE J. Solid State Circuits, 2002
Proceedings of the 35th Annual International Symposium on Microarchitecture, 2002
Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002
Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002
2001
IEEE J. Solid State Circuits, 2001
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001
Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, 2001
1998
Decreasing low-voltage manufacturing-induced delay variations with adaptive mixed-voltage-swing circuits.
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998
A low-power 16-bit multiplier-accumulator using series-regulated mixed swing techniques.
Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, 1998
1997
IEEE Trans. Very Large Scale Integr. Syst., 1997
1996
Holistic handwritten word recognition using temporal features derived from off-line images.
Pattern Recognit. Lett., 1996
Static power driven voltage scaling and delay driven buffer sizing in mixed swing QuadRail for sub-1V I/O swings.
Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996
1995
Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995