Shekhar Borkar
Affiliations:- Qualcomm
- Intel Corporation, Circuit Research Lab, Hillsboro, OR, USA
According to our database1,
Shekhar Borkar
authored at least 116 papers
between 1988 and 2021.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 2009, "For contributions to low power digital circuits in deep submicron technology".
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
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on linkedin.com
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on intel.com
On csauthors.net:
Bibliography
2021
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021
2017
Parallel Comput., 2017
2016
Proceedings of the Near Threshold Computing, Technology, Methods and Applications., 2016
2015
A 340 mV-to-0.9 V 20.2 Tb/s Source-Synchronous Hybrid Packet/Circuit-Switched 16 × 16 Network-on-Chip in 22 nm Tri-Gate CMOS.
IEEE J. Solid State Circuits, 2015
Circuits evening panel discussion 1: Is university circuit design research and education keeping up with industry needs?
Proceedings of the Symposium on VLSI Circuits, 2015
2014
16.1 A 340mV-to-0.9V 20.2Tb/s source-synchronous hybrid packet/circuit-switched 16×16 network-on-chip in 22nm tri-gate CMOS.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
Characterization of radiation-induced SRAM and logic soft errors from 0.33V to 1.0V in 65nm CMOS.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
2013
A 2.05 GVertices/s 151 mW Lighting Accelerator for 3D Graphics Vertex and Pixel Shading in 32 nm CMOS.
IEEE J. Solid State Circuits, 2013
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
Proceedings of the 27th IEEE International Symposium on Parallel and Distributed Processing, 2013
Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture, 2013
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
2012
A 2.8GHz 128-entry × 152b 3-read/2-write multi-precision floating-point register file and shuffler in 32nm CMOS.
Proceedings of the Symposium on VLSI Circuits, 2012
A 2.05GVertices/s 151mW lighting accelerator for 3D graphics vertex and pixel shading in 32nm CMOS.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
Session 18 overview: Innovative circuits in emerging technologies: Technology directions subcommittee.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
A 1.45GHz 52-to-162GFLOPS/W variable-precision floating-point fused multiply-add unit with certainty tracking in 32nm CMOS.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
Proceedings of the Transition of HPC Towards Exascale Computing, 2012
Proceedings of the 49th Annual Design Automation Conference 2012, 2012
2011
A 48-Core IA-32 Processor in 45 nm CMOS Using On-Die Message-Passing and DVFS for Performance and Power Scaling.
IEEE J. Solid State Circuits, 2011
Within-Die Variation-Aware Dynamic-Voltage-Frequency-Scaling With Optimal Core Allocation and Thread Hopping for the 80-Core TeraFLOPS Processor.
IEEE J. Solid State Circuits, 2011
Microprocessor system applications and challenges for through-silicon-via-based three-dimensional integration.
IET Comput. Digit. Tech., 2011
Proceedings of the 2011 International Symposium on Physical Design, 2011
Proceedings of the 2011 IEEE Hot Chips 23 Symposium (HCS), 2011
Proceedings of the 48th Design Automation Conference, 2011
Hybrid Circuit/Packet Switched Network for Energy Efficient on-Chip Interconnections.
Proceedings of the Low Power Networks-on-Chip., 2011
2010
A 300 mV 494GOPS/W Reconfigurable Dual-Supply 4-Way SIMD Vector Processing Accelerator in 45 nm CMOS.
IEEE J. Solid State Circuits, 2010
Proceedings of the International Workshop on System Level Interconnect Prediction Workshop, 2010
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
Within-die variation-aware dynamic-voltage-frequency scaling core mapping and thread hopping for an 80-core processor.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
A 4.1Tb/s bisection-bandwidth 560Gb/s/W streaming circuit-switched 8×8 mesh network-on-chip in 45nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
A 320mV-to-1.2V on-die fine-grained reconfigurable fabric for DSP/media accelerators in 32nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
2009
2 GHz 2 Mb 2T Gain Cell Memory Macro With 128 GBytes/sec Bandwidth in a 65 nm Logic Process Technology.
IEEE J. Solid State Circuits, 2009
A 320 mV 56 μW 411 GOPS/Watt Ultra-Low Voltage Motion Estimation Accelerator in 65 nm CMOS.
IEEE J. Solid State Circuits, 2009
A 300mV 494GOPS/W reconfigurable dual-supply 4-Way SIMD vector processing accelerator in 45nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
Proceedings of the 46th Design Automation Conference, 2009
Proceedings of the 46th Design Automation Conference, 2009
2008
IEEE J. Solid State Circuits, 2008
IEEE J. Solid State Circuits, 2008
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
A 320mV 56μW 411GOPS/Watt Ultra-Low Voltage Motion Estimation Accelerator in 65nm CMOS.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
Proceedings of the ESSCIRC 2008, 2008
Proceedings of the 45th Design Automation Conference, 2008
2007
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
Proceedings of the 44th Design Automation Conference, 2007
2006
A process variation compensating technique with an on-die leakage current sensor for nanometer scale dynamic circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2006
IEEE J. Solid State Circuits, 2006
Proceedings of the VLSI-SoC: Research Trends in VLSI and Systems on Chip, 2006
Introduction to panel discussion Probabilistic & statistical design - the wave of the future.
Proceedings of the IFIP VLSI-SoC 2006, 2006
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
Proceedings of the 43rd Design Automation Conference, 2006
Proceedings of the 43rd Design Automation Conference, 2006
2005
Designing Reliable Systems from Unreliable Components: The Challenges of Transistor Variability and Degradation.
IEEE Micro, 2005
IEEE J. Solid State Circuits, 2005
A 3.6-Gb/s point-to-point heterogeneous-voltage-capable DRAM interface for capacity-scalable memory subsystems.
IEEE J. Solid State Circuits, 2005
A 233-MHz 80%-87% efficient four-phase DC-DC converter utilizing air-core inductors on package.
IEEE J. Solid State Circuits, 2005
IEEE J. Solid State Circuits, 2005
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005
An 8.3GHz dual supply/threshold optimized 32b integer ALU-register file loop in 90nm CMOS.
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005
2004
Full-chip subthreshold leakage power prediction and reduction techniques for sub-0.18-μm CMOS.
IEEE J. Solid State Circuits, 2004
Measurements and analysis of SER-tolerant latch in a 90-nm dual-V<sub>T</sub> CMOS process.
IEEE J. Solid State Circuits, 2004
Proceedings of the 37th Annual International Symposium on Microarchitecture (MICRO-37 2004), 2004
Proceedings of the 33rd European Solid-State Circuits Conference, 2004
Proceedings of the 41th Design Automation Conference, 2004
Proceedings of the 41th Design Automation Conference, 2004
2003
ACM Queue, 2003
Dynamic sleep transistor and body bias for active leakage power control of microprocessors.
IEEE J. Solid State Circuits, 2003
IEEE J. Solid State Circuits, 2003
IEEE J. Solid State Circuits, 2003
A 4.5-GHz 130-nm 32-KB L0 cache with a leakage-tolerant self reverse-bias bitline scheme.
IEEE J. Solid State Circuits, 2003
IEEE J. Solid State Circuits, 2003
Exponential Challenges, Exponential Rewards - The future of Moore's Law.
Proceedings of the IFIP VLSI-SoC 2003, 2003
Effectiveness and scaling trends of leakage control techniques for sub-130nm CMOS technologies.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003
Proceedings of the ESSCIRC 2003, 2003
Proceedings of the ESSCIRC 2003, 2003
Proceedings of the 40th Design Automation Conference, 2003
Proceedings of the 40th Design Automation Conference, 2003
Proceedings of the IEEE Custom Integrated Circuits Conference, 2003
2002
Analysis of dual-V<sub>T</sub> SRAM cells with full-swing single-ended bit line sensing for on-chip cache.
IEEE Trans. Very Large Scale Integr. Syst., 2002
IEEE J. Solid State Circuits, 2002
IEEE J. Solid State Circuits, 2002
Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002
Proceedings of the 39th Design Automation Conference, 2002
Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors.
Proceedings of the 39th Design Automation Conference, 2002
Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002
Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002
2001
Comparative delay and energy of single edge-triggered & dual edge-triggered pulsed flip-flops for high-performance microprocessors.
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001
Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, 2001
Proceedings of the 38th Design Automation Conference, 2001
Proceedings of ASP-DAC 2001, 2001
2000
Proceedings of the 10th ACM Great Lakes Symposium on VLSI 2000, 2000
1999
IEEE J. Solid State Circuits, 1999
Technology scaling behavior of optimum reverse body bias for standby leakage power reduction in CMOS IC's.
Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999
Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999
1995
IEEE J. Solid State Circuits, December, 1995
1990
Proceedings of the 17th Annual International Symposium on Computer Architecture, 1990
1988
Proceedings of the Proceedings Supercomputing '88, Orlando, FL, USA, November 12-17, 1988, 1988