Martin Anderson

According to our database¹, Martin Anderson authored at least 18 papers between 2003 and 2023.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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PhD thesis

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On csauthors.net:

Bibliography

2023

A 12/16 GSps Time-Interleaved Pipelined-SAR ADC with Temperature Robust Performance at 0.75V Supply in 7nm FinFET Technology.

[BibT_eX]

[DOI]

Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023

2022

A Bang-Bang Digital PLL Covering 11.1-14.3 GHz and 14.7-18.7 GHz with sub-40 fs RMS Jitter in 7 nm FinFET Technology.

[BibT_eX]

[DOI]

Aravind Tharayil Narayanan

Martin Anderson

Hind Dafallah

Mesrop Daghbashyan

Tayebeh Ghanavati Nejad

Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022

2014

A Filtering ΔΣ ADC for LTE and Beyond.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2014

A low-power 2nd-order CT ΔΣ modulator with an asynchronous SAR quantizer.

[BibT_eX]

[DOI]

Proceedings of the 2014 NORCHIP, Tampere, Finland, October 27-28, 2014, 2014

An 11mW continuous time delta-Sigma modulator with 20 MHz bandwidth in 65nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013

Complex IF Harmonic Rejection Mixer for Non-Contiguous Dual Carrier Reception in 65 nm CMOS.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2013

Design of a Configurable Complex IF Receiver Supporting LTE Carrier Aggregation.

[BibT_eX]

[DOI]

Proceedings of the 77th IEEE Vehicular Technology Conference, 2013

A low-power 2nd-order CT ΔΣ modulator with a single operational amplifier.

[BibT_eX]

[DOI]

Proceedings of the 2013 NORCHIP, Vilnius, Lithuania, November 11-12, 2013, 2013

A receiver for LTE Rel-11 and beyond supporting non-contiguous carrier aggregation.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

A 9MHz filtering ADC with additional 2<sup>nd</sup>-order ΔΣ modulator noise suppression.

[BibT_eX]

[DOI]

Proceedings of the ESSCIRC 2013, 2013

2012

A 4.75-34.75 MHz digitally tunable active-RC LPF for >60dB mean RX IRR in 65nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the 38th European Solid-State Circuit conference, 2012

2011

A continuous time ΔΣ modulator with reduced clock jitter sensitivity through DSCR feedback.

[BibT_eX]

[DOI]

Proceedings of the 2011 NORCHIP, Lund, Sweden, November 14-15, 2011, 2011

A 9-band WCDMA/EDGE transceiver supporting HSPA evolution.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2010

Impact of MOS threshold-voltage mismatch in current-steering DACs for CT ΣΔ modulators.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009

DT Modeling of Clock Phase-Noise Effects in LP CT DeltaSigma ADCs With RZ Feedback.

[BibT_eX]

[DOI]

Martin Anderson

Lars Sundström

IEEE Trans. Circuits Syst. II Express Briefs, 2009

Design and Measurement of a CT ΔΣ ADC With Switched-Capacitor Switched-Resistor Feedback.

[BibT_eX]

[DOI]

Martin Anderson

Lars Sundström

IEEE J. Solid State Circuits, 2009

2007

A 312-MHz CT Δ∑ modulator using a SC feedback DAC with reduced peak current.

[BibT_eX]

[DOI]

Martin Anderson

Lars Sundström

Proceedings of the 33rd European Solid-State Circuits Conference, 2007

2003

Verification of a blind mismatch error equalization method for randomly interleaved ADCs using a 2.5V/12b/30MSs PSAADC.

[BibT_eX]

[DOI]

Proceedings of the ESSCIRC 2003, 2003

Martin Anderson

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