Peter-Michael Seidel

Affiliations:
  • University of Hawaii at Manoa, Honolulu, HI, USA
  • Southern Methodist University, Dallas, Texas, USA
  • Saarland University, Saarbrücken, Germany


According to our database1, Peter-Michael Seidel authored at least 37 papers between 1998 and 2019.

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Bibliography

2019
Privacy Protocols.
Proceedings of the Foundations of Security, Protocols, and Equational Reasoning, 2019

2018
Variable Latency Division.
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

High-Performance Multiplication Modulo 2<sup>n</sup> - 3.
Proceedings of the 52nd Asilomar Conference on Signals, Systems, and Computers, 2018

2017
Modeling and Analysis of Secure Processor Extensions Based on Actor Networks.
Proceedings of the 18th International Workshop on Microprocessor and SOC Test and Verification, 2017

Quotients in monadic programming: Projective algebras are equivalent to coalgebras.
Proceedings of the 32nd Annual ACM/IEEE Symposium on Logic in Computer Science, 2017

2016
(Modular) Effect Algebras are Equivalent to (Frobenius) Antispecial Algebras.
Proceedings of the Proceedings 13th International Conference on Quantum Physics and Logic, 2016

2015
Modeling and Analysis of Trusted Boot Processes Based on Actor Network Procedures.
Proceedings of the 16th International Workshop on Microprocessor and SOC Test and Verification, 2015

A parametric error analysis of Goldschmidt's square-root algorithm.
Proceedings of the 49th Asilomar Conference on Signals, Systems and Computers, 2015

2014
Guest Editors' Introduction: Special Section on Computer Arithmetic.
IEEE Trans. Computers, 2014

A Case for Multi-level Combination of Theorem Proving and Model Checking Tools.
Proceedings of the 15th International Microprocessor Test and Verification Workshop, 2014

Directed Test Case Generation for x86 Instruction Decoding.
Proceedings of the 15th International Microprocessor Test and Verification Workshop, 2014

2013
The Floating-Point Unit of the Jaguar x86 Core.
Proceedings of the 21st IEEE Symposium on Computer Arithmetic, 2013

2011
Formal Verification of an Iterative Low-Power x86 Floating-Point Multiplier with Redundant Feedback
Proceedings of the Proceedings 10th International Workshop on the ACL2 Theorem Prover and its Applications, 2011

2010
Welcome to ICCD 2010!
Proceedings of the 28th International Conference on Computer Design, 2010

2007
An FPGA implementation of pipelined multiplicative division with IEEE Rounding.
Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, 2007

An FPGA Implementation of a Fully Verified Double Precision IEEE Floating-Point Adder.
Proceedings of the IEEE International Conference on Application-Specific Systems, 2007

2006
Optimized Arithmetic Hardware Design based on Hierarchical Formal Verification.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

2005
Secondary Radix Recodings for Higher Radix Multipliers.
IEEE Trans. Computers, 2005

A parametric error analysis of Goldschmidt's division algorithm.
J. Comput. Syst. Sci., 2005

Formal Verification of Parametric Multiplicative Division Implementations.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Challenges in the Formal Verification of Complete State-of-the-Art Processors.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

High-Radix Implementation of IEEE Floating-Point Addition.
Proceedings of the 17th IEEE Symposium on Computer Arithmetic (ARITH-17 2005), 2005

2004
Delay-Optimized Implementation of IEEE Floating-Point Addition.
IEEE Trans. Computers, 2004

Two-Dimensional Folding Strategies for Improved Layouts of Cyclic Shifters.
Proceedings of the 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), 2004

Formal Hardware Verification based on Signal Correlation Properties.
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

Design of an On-Line IEEE Floating-Point Addition Unit for FPGAs.
Proceedings of the 12th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2004), 2004

2003
Pipelined Multiplicative Division with IEEE Rounding.
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

2002
To Booth or not to Booth.
Integr., 2002

2001
How to Half Wire Lengths in the Layout of Cyclic Shifter.
Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

Binary Multiplication Radix-32 and Radix-256.
Proceedings of the 15th IEEE Symposium on Computer Arithmetic (Arith-15 2001), 2001

On the Design of Fast IEEE Floating-Point Adders.
Proceedings of the 15th IEEE Symposium on Computer Arithmetic (Arith-15 2001), 2001

2000
A Comparison of Three Rounding Algorithms for IEEE Floating-Point Multiplication.
IEEE Trans. Computers, 2000

A dual precision IEEE floating-point multiplier.
Integr., 2000

1999
On the design of IEEE compliant floating point units and their quantitative analysis.
PhD thesis, 1999

High-speed redundant reciprocal approximation.
Integr., 1999

1998
How many logic levels does floating-point addition require?
Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998

How to Half the Latency of IEEE Compliant Floating-Point Multiplication.
Proceedings of the 24th EUROMICRO '98 Conference, 1998


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