Alberto Nannarelli

According to our database1, Alberto Nannarelli authored at least 58 papers between 1996 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Bibliography

2019
Tunable Floating-Point Adder.
IEEE Trans. Computers, 2019

A Reinforcement Learning-Based QAM/PSK Symbol Synchronizer.
IEEE Access, 2019

2018
Tunable Floating-Point for Embedded Machine Learning Algorithms Implementation.
Proceedings of the 15th International Conference on Synthesis, 2018

Digital Architecture and ASIC Implementation of Wideband Delta DOR Spacecraft Onboard Tracker.
Proceedings of the 15th International Conference on Synthesis, 2018

Tunable Floating-Point for Artificial Neural Networks.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

Tunable Floating-Point for Energy Efficient Accelerators.
Proceedings of the 25th IEEE Symposium on Computer Arithmetic, 2018

A Power Efficient Digital Front-End for Cognitive Radio Systems.
Proceedings of the 52nd Asilomar Conference on Signals, Systems, and Computers, 2018

2017
Improved 64-bit Radix-16 Booth Multiplier Based on Partial Product Array Height Reduction.
IEEE Trans. on Circuits and Systems, 2017

Robust throughput boosting for low latency dynamic partial reconfiguration.
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017

A multi-format floating-point multiplier for power-efficient operations.
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017

2016
Performance/Power Space Exploration for Binary64 Division Units.
IEEE Trans. Computers, 2016

Design and simulation of a quaternary memory cell based on a physical memristor.
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2016

A hardware framework for on-chip FPGA acceleration.
Proceedings of the International Symposium on Integrated Circuits, 2016

Dynamically-loaded Hardware Libraries (HLL) technology for audio applications.
Proceedings of the 50th Asilomar Conference on Signals, Systems and Computers, 2016

2015
Power and Thermal Efficient Numerical Processing.
Proceedings of the Handbook on Data Centers, 2015

Thermal aware floorplanning incorporating temperature dependent wire delay estimation.
Microprocessors and Microsystems - Embedded Hardware Design, 2015

A framework for dynamically-loaded hardware library (HLL) in FPGA acceleration.
Proceedings of the IEEE International Symposium on Signal Processing and Information Technology, 2015

2014
Guest Editors' Introduction: Special Section on Computer Arithmetic.
IEEE Trans. Computers, 2014

Decimal engine for energy-efficient multicore processors.
Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014

Energy efficient FPGA based hardware accelerators for financial applications.
Proceedings of the 2014 NORCHIP, Tampere, Finland, October 27-28, 2014, 2014

Twenty years of research on RNS for DSP: Lessons learned and future perspectives.
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

2013
Layout-Driven Post-Placement Techniques for Temperature Reduction and Thermal Gradient Minimization.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2013

Truncated multipliers through power-gating for degrading precision arithmetic.
Proceedings of the 2013 Asilomar Conference on Signals, 2013

2012
Power Efficient Division and Square Root Unit.
IEEE Trans. Computers, 2012

Comments on 'improving the speed of decimal division'.
IET Computers & Digital Techniques, 2012

Design of power efficient FPGA based hardware accelerators for financial applications.
Proceedings of the NORCHIP 2012, Copenhagen, Denmark, November 12-13, 2012, 2012

Power efficient design of parallel/serial FIR filters in RNS.
Proceedings of the Conference Record of the Forty Sixth Asilomar Conference on Signals, 2012

Imprecise arithmetic for low power image processing.
Proceedings of the Conference Record of the Forty Sixth Asilomar Conference on Signals, 2012

2011
FPGA Based Acceleration of Decimal Operations.
Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011

Temperature dependent wire delay estimation in floorplanning.
Proceedings of the 2011 NORCHIP, Lund, Sweden, November 14-15, 2011, 2011

FPGA implementation of decimal processors for hardware acceleration.
Proceedings of the 2011 NORCHIP, Lund, Sweden, November 14-15, 2011, 2011

Radix-16 Combined Division and Square Root Unit.
Proceedings of the 20th IEEE Symposium on Computer Arithmetic, 2011

2010
Post-placement temperature reduction techniques.
Proceedings of the Design, Automation and Test in Europe, 2010

Power dissipation challenges in multicore floating-point units.
Proceedings of the 21st IEEE International Conference on Application-specific Systems Architectures and Processors, 2010

2009
On-chip Thermal Modeling Based on SPICE Simulation.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009

Division Unit for Binary Integer Decimals.
Proceedings of the 20th IEEE International Conference on Application-Specific Systems, 2009

2008
On the Comparison of Different Number Systems in the Implementation of Complex FIR Filters.
Proceedings of the VLSI-SoC: Design Methodologies for SoC and SiP, 2008

A variant of a radix-10 combinational multiplier.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

ADAPTO: full-adder based reconfigurable architecture for bit level operations.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

2007
A Radix-10 Digit-Recurrence Division Unit: Algorithm and Architecture.
IEEE Trans. Computers, 2007

Low-power adaptive filter based on RNS components.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2005
Digit-Recurrence Dividers with Reduced Logical Depth.
IEEE Trans. Computers, 2005

Programmable power-of-two RNS scaler and its application to a QRNS polyphase filter.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Low Latency Digit-Recurrence Reciprocal and Square-Root Reciprocal Algorithm and Architecture.
Proceedings of the 17th IEEE Symposium on Computer Arithmetic (ARITH-17 2005), 2005

2004
Low-power implementation of polyphase filters in Quadratic Residue Number system.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A Tool for Automatic Generation of RTL-Level VHDL Description of RNS FIR Filters.
Proceedings of the 2004 Design, 2004

2003
Power-delay tradeoffs in residue number system.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2002
Power characterization of digital filters implemented on FPGA.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Fast Radix-4 Retimed Division with Selection by Comparisons.
Proceedings of the 13th IEEE International Conference on Application-Specific Systems, 2002

2001
Cached-code compression for energy minimization in embedded processors.
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

FPGA realization of RNS to binary signed conversion architecture.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Tradeoffs between residue number system and traditional FIR filters.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

1999
Low-Power Divider.
IEEE Trans. Computers, 1999

Low-Power Radix-4 Combined Division and Square Root.
Proceedings of the IEEE International Conference On Computer Design, 1999

Low-Power Division: Comparison among Implementations of Radix 4, 8 and 16.
Proceedings of the 14th IEEE Symposium on Computer Arithmetic (Arith-14 '99), 1999

1998
Power-delay tradeoffs for radix-4 and radix-8 dividers.
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998

Low-power radix-8 divider.
Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998

1996
Low-power radix-4 divider.
Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996


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