Tushar Gupta

Orcid: 0009-0003-0903-5867

According to our database1, Tushar Gupta authored at least 21 papers between 2009 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
Precision at its Core: Machine Learning-Infused Metabolomics Model for Preterm Birth Prediction in Human.
Proceedings of the 14th International Conference on Computing Communication and Networking Technologies, 2023

Ontology-based Evaluation of ABAC Policies for Inter-Organizational Resource Sharing.
Proceedings of the 9th ACM International Workshop on Security and Privacy Analytics, 2023

2022
Poster: ASQL - Attribute Based Access Control Extension for SQL.
Proceedings of the SACMAT '22: The 27th ACM Symposium on Access Control Models and Technologies, New York, NY, USA, June 8, 2022

2021
"A Helping Hand": Design and Evaluation of a Reading Assistant Application for Children with Dyslexia.
Proceedings of the OzCHI '21: 33rd Australian Conference on Human-Computer Interaction, Melbourne, VI, Australia, 30 November 2021, 2021

Augmenta11y: A Reading Assistant Application for Children with Dyslexia.
Proceedings of the ASSETS '21: The 23rd International ACM SIGACCESS Conference on Computers and Accessibility, 2021

2020
Vesti: Energy-Efficient In-Memory Computing Accelerator for Deep Neural Networks.
IEEE Trans. Very Large Scale Integr. Syst., 2020

Inception C-Net(IC-Net): Altered Inception Module for Detection of Covid-19 and Pneumonia using Chest X-rays.
Proceedings of the 15th IEEE International Conference on Industrial and Information Systems, 2020

2019
Role of Big Data Analytics In Banking.
Proceedings of the International Conference on contemporary Computing and Informatics, 2019

Vesti: An In-Memory Computing Processor for Deep Neural Networks Acceleration.
Proceedings of the 53rd Asilomar Conference on Signals, Systems, and Computers, 2019

2017
BrainSegNet : A Segmentation Network for Human Brain Fiber Tractography Data into Anatomically Meaningful Clusters.
CoRR, 2017

2016
Error Correction Code protected Data Processing Units.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016

Flexible, Cost-Efficient, High-Throughput Architecture for Layered LDPC Decoders with Fully-Parallel Processing Units.
Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016

2015
Crime detection and criminal identification in India using data mining techniques.
AI Soc., 2015

SHIM: A Novel Influence Maximization Algorithm for Targeted Marketing.
Proceedings of the Mining Intelligence and Knowledge Exploration, 2015

2014
Optimized Simulation Acceleration with Partial Testbench Evaluation.
Proceedings of the 15th International Microprocessor Test and Verification Workshop, 2014

2012
Impact of Power Consumption and Temperature on Processor Lifetime Reliability.
J. Low Power Electron., 2012

Efficient Online RTL Debugging Methodology for Logic Emulation Systems.
Proceedings of the 25th International Conference on VLSI Design, 2012

Fast and scalable hybrid functional verification and debug with dynamically reconfigurable co-simulation.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

2011
A scalable hybrid verification system based on HDL slicing.
Proceedings of the 2011 IEEE International High Level Design Validation and Test Workshop, 2011

2010
High Level Power and Energy Exploration Using ArchC.
Proceedings of the 22st International Symposium on Computer Architecture and High Performance Computing, 2010

2009
Nonlinear acoustic echo control using an accelerometer.
Proceedings of the IEEE International Conference on Acoustics, 2009


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