Arindam Sanyal

According to our database1, Arindam Sanyal authored at least 52 papers between 2009 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2020
Unified Analog PUF and TRNG Based on Current-Steering DAC and VCO.
IEEE Trans. Very Large Scale Integr. Syst., 2020

0.3 pJ/Bit Machine Learning Resistant Strong PUF Using Subthreshold Voltage Divider Array.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

0.6-1.2 V, 0.22 pJ/bit True Random Number Generator Based on SAR ADC.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

76-dB DR, 48 fJ/Step Second-Order VCO-Based Current-to-Digital Converter.
IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 2020

0.13pW/Hz Ring VCO-Based Continuous-Time Read-Out ADC for Bio-Impedance Measurement.
IEEE Trans. Circuits Syst., 2020

8fJ/Step Bandpass ADC With Digitally Assisted NTF Re-Configuration.
IEEE Trans. Circuits Syst., 2020

A Fractional-<i>N</i> PLL With Space-Time Averaging for Quantization Noise Reduction.
IEEE J. Solid State Circuits, 2020

Deep SCNN-Based Real-Time Object Detection for Self-Driving Vehicles Using LiDAR Temporal Data.
IEEE Access, 2020

Neural Networks for Authenticating Integrated Circuits Based on Intrinsic Nonlinearity.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

Digital Machine Learning Circuit for Real-Time Stress Detection from Wearable ECG Sensor.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

2019
Highly Digital Second-Order $\Delta\Sigma$ VCO ADC.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Maximum Likelihood Estimation-Based SAR ADC.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

Advances in Voltage-Controlled-Oscillator-Based ΔΣ ADCs.
IEICE Trans. Electron., 2019

39fJ Analog Artificial Neural Network for Breast Cancer Classification in 65nm CMOS.
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

A 0.36pJ/bit Analog PUF Based on Current Steering DAC and VCO.
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

Fully Digital 1-1 MASH VCO-Based ADC Architecture.
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

A Highly Digital CCO-Based Asynchronous Analog-to-Time Converter.
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

A Single Channel Bandpass SAR ADC with Digitally Assisted NTF Re-configuration.
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

A Machine Learning Resistant Strong PUF using Subthreshold Voltage Divider Array in 65nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Common-Source Amplifier Based Analog Artificial Neural Network Classifier.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

0.43nJ, 0.48pJ/step Second-Order ΔΣ Current-to-Digital Converter for IoT Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Ultra-Low Power Analog Multiplier Based on Translinear Principle.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

A 2.4-GHz ΔΣ Fractional-N Synthesizer with Space-Time Averaging for Noise Reduction.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

8.6fJ/step VCO-Based CT 2<sup>nd</sup>-Order $\Delta\Sigma$ ADC.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019

2018
Physically Unclonable Function based on Voltage Divider Arrays in Subthreshold Region.
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

A Digital PLL Based 2<sup>nd</sup>-Order Δ∑ Bandpass Time-Interleaved ADC.
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

Low-power Scaling-friendly Ring Oscillator based ΔΣ ADC.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Ring Oscillator Based Delta-Sigma ADCs.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

A Second-Order Purely VCO-Based CT Δ∑ ADC Using a Modified DPLL in 40-nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018

2017
A 0.95-mW 6-b 700-MS/s Single-Channel Loop-Unrolled SAR ADC in 40-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

An Energy-Efficient Hybrid SAR-VCO ΔΣ Capacitance-to-Digital Converter in 40-nm CMOS.
IEEE J. Solid State Circuits, 2017

A 0.7-V 0.6-µW 100-kS/s Low-Power SAR ADC With Statistical Estimation-Based Noise Reduction.
IEEE J. Solid State Circuits, 2017

2<sup>nd</sup>-Order VCO-based CT ΔΣ ADC architecture.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

2016
An Energy-Efficient VCO-Based Matrix Multiplier Block to Support On-Chip Image Analysis.
CoRR, 2016

A 18.5-fJ/step VCO-based 0-1 MASH ΔΣ ADC with digital background calibration.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

Comparator common-mode variation effects analysis and its application in SAR ADCs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

A 55fJ/conv-step hybrid SAR-VCO ΔΣ capacitance-to-digital converter in 40nm CMOS.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016

2015
Dynamic Element Matching With Signal-Independent Element Transition Rates for Multibit ΔΣ Modulators.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

A Novel Hybrid Radix-3/Radix-2 SAR ADC With Fast Convergence and Low Hardware Complexity.
IEEE Trans. Circuits Syst. II Express Briefs, 2015

Digital Background Calibration for Pipelined ADCs Based on Comparator Decision Time Quantization.
IEEE Trans. Circuits Syst. II Express Briefs, 2015

Dynamic Element Matching Techniques for Static and Dynamic Errors in Continuous-Time Multi-Bit ΔΣ Modulators.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2015

A 10.5-b ENOB 645 nW 100kS/s SAR ADC with statistical estimation based noise reduction.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

2014
A Thermometer-Like Mismatch Shaping Technique With Minimum Element Transition Activity for Multibit ΔΣ DACs.
IEEE Trans. Circuits Syst. II Express Briefs, 2014

An Energy-Efficient Low Frequency-Dependence Switching Technique for SAR ADCs.
IEEE Trans. Circuits Syst. II Express Briefs, 2014

An enhanced ISI shaping technique for multi-bit ΔΣ DACs.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

A low frequency-dependence, energy-efficient switching technique for bottom-plate sampled SAR ADC.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

A 24-µW 11-bit 1-MS/s SAR ADC with a bidirectional single-side switching technique.
Proceedings of the ESSCIRC 2014, 2014

A hybrid SAR-VCO ΔΣ ADC with first-order noise shaping.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2013
A very high energy-efficiency switching technique for SAR ADCs.
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

A single SAR ADC converting multi-channel sparse signals.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2012
A simple and efficient dithering method for vector quantizer based mismatch-shaped ΔΣ DACs.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2009
An Efficient Time Domain Speech Compression Algorithm Based on LPC and Sub-Band Coding Techniques.
J. Commun., 2009


  Loading...