Philipp V. Panitz

According to our database, Philipp V. Panitz authored at least 4 papers between 2007 and 2011.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2011

A gate sizing method for glitch power reduction.

Lei Wang, Markus Olbrich, Erich Barke, Thomas Büchner, Markus Bühler, Philipp V. Panitz

Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011

A theoretical probabilistic simulation framework for dynamic power estimation.

Lei Wang, Markus Olbrich, Erich Barke, Thomas Büchner, Markus Bühler, Philipp V. Panitz

Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

2008

Considering possible opens in non-tree topology wire delay calculation.

Philipp V. Panitz, Markus Olbrich, Erich Barke, Markus Bühler, Jürgen Koehl

Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

2007

Robust wiring networks for DfY considering timing constraints.

Philipp V. Panitz, Markus Olbrich, Erich Barke, Jürgen Koehl

Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007