Erich Barke

According to our database, Erich Barke authored at least 84 papers between 1983 and 2019.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2019

Hierarchical Verification of AMS Systems With Affine Arithmetic Decision Diagrams.

Carna Zivkovic, Christoph Grimm, Markus Olbrich, Oliver Scharf, Erich Barke

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

2018

STP - A Quadratic VLSI Placement Tool Using Graphic Processing Units.

Bjorn Bredthauer, Markus Olbrich, Erich Barke

Proceedings of the 17th International Symposium on Parallel and Distributed Computing, 2018

2016

Embedded tutorial: Analog-/mixed-signal verification methods for AMS coverage analysis.

Erich Barke, Andreas Furtig, Georg Glaeser, Christoph Grimm, Lars Hedrich, Stefan Heinen, Eckhard Hennig, Hyun-Sek Lukas Lee, Wolfgang Nebel, Gregor Nitsche, Markus Olbrich, Carna Radojicic, Fabian Speicher

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015

Fast global interconnnect driven 3D floorplanning.

Artur Quiring, Markus Olbrich, Erich Barke

Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015

Split and merge strategies for solving uncertain equations using affine arithmetic.

Oliver Scharf, Markus Olbrich, Erich Barke

Proceedings of the 8th International Conference on Simulation Tools and Techniques, 2015

Automated generation of hybrid system models for reachability analysis of nonlinear analog circuits.

Hyun-Sek Lukas Lee, Matthias Althoff, Stefan Hoelldampf, Markus Olbrich, Erich Barke

Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014

Simulation Based Verification with Range Based Signal Representations for Mixed-Signal Systems.

Michael Kärgel, Markus Olbrich, Erich Barke

Proceedings of the 27th Symposium on Integrated Circuits and Systems Design, 2014

Application of Mission Profiles to enable cross-domain constraint-driven design.

C. Katzschke, M.-P. Sohn, Markus Olbrich, Volker Meyer zu Bexten, Markus Tristl, Erich Barke

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013

Improving 3D-Floorplanning using smart selection operations in meta-heuristic optimization.

Artur Quiring, Markus Olbrich, Erich Barke

Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013

2012

Efficient generation of analog circuit models for accelerated mixed-signal simulation.

Stefan Hoelldampf, Hyun-Sek Lukas Lee, Daniel Zaum, Markus Olbrich, Erich Barke

Proceedings of the IEEE 25th International SOC Conference, 2012

2011

A Statistical Learning Based Modeling Approach and Its Application in Leakage Library Characterization.

Min Zhang, R. Häußler, Markus Olbrich, Harald Kinzelbach, Erich Barke

Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011

A gate sizing method for glitch power reduction.

Lei Wang, Markus Olbrich, Erich Barke, Thomas Büchner, Markus Bühler, Philipp V. Panitz

Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011

Using analog circuit behavior to generate SystemC events for an acceleration of mixed-signal simulation.

Stefan Hoelldampf, Daniel Zaum, Markus Olbrich, Erich Barke

Proceedings of the IEEE 29th International Conference on Computer Design, 2011

A theoretical probabilistic simulation framework for dynamic power estimation.

Lei Wang, Markus Olbrich, Erich Barke, Thomas Büchner, Markus Bühler, Philipp V. Panitz

Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

3D floorplanning considering vertically aligned rectilinear modules using T^∗-tree.

Artur Quiring, Marc Lindenberg, Markus Olbrich, Erich Barke

Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

2010

An Accelerated Mixed-Signal Simulation Kernel for SystemC.

Daniel Zaum, Stefan Hoelldampf, Markus Olbrich, Erich Barke, Ingmar Neumann

Proceedings of the 2010 Forum on specification & Design Languages, 2010

Towards Abstract Analysis Techniques for Range Based System Simulations.

Florian Schupfer, Christoph Grimm, Markus Olbrich, Michael Kärgel, Erich Barke

Proceedings of the 2010 Forum on specification & Design Languages, 2010

2009

Fast dynamic power estimation considering glitch filtering.

Lei Wang, Markus Olbrich, Erich Barke, Thomas Büchner, Markus Bühler

Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

Formal approaches to analog circuit verification.

Erich Barke, Darius Grabowski, Helmut Graeb, Lars Hedrich, Stefan Heinen, Ralf Popp, Sebastian Steinhorst, Yifan Wang

Proceedings of the Design, Automation and Test in Europe, 2009

The PRAISE approach for accelerated transient analysis applied to wire models.

Daniel Zaum, Stefan Hoelldampf, Markus Olbrich, Erich Barke, Ingmar Neumann, Sebastian Schmidt

Proceedings of the 2009 IEEE International Behavioral Modeling and Simulation Workshop, 2009

2008

Considering possible opens in non-tree topology wire delay calculation.

Philipp V. Panitz, Markus Olbrich, Erich Barke, Markus Bühler, Jürgen Koehl

Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

Methodologies for High-Level Modelling and Evaluation in the Automotive Domain (invited).

Stefan Hoelldampf, Daniel Zaum, Markus Olbrich, Erich Barke, Ingmar Neumann, Sebastian Schmidt

Proceedings of the Forum on specification and Design Languages, 2008

A Trapezoidal Approach to Corner Stitching Data Structures for Arbitrary Routing Angles.

Thomas Jambor, Daniel Zaum, Markus Olbrich, Erich Barke

Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008

Determining the Technical Complexity of Integrated Circuits.

Peter Leppelt, Erich Barke

Proceedings of the Design, Automation and Test in Europe, 2008

Distribution arithmetic for stochastical analysis.

Markus Olbrich, Erich Barke

Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

Analog circuit simulation using range arithmetics.

Darius Grabowski, Markus Olbrich, Erich Barke

Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007

Algorithms for automatic length compensation of busses in analog integrated circuits.

Matthew A. Smith, Lars A. Schreiner, Erich Barke, Volker Meyer zu Bexten

Proceedings of the 2007 International Symposium on Physical Design, 2007

Robust wiring networks for DfY considering timing constraints.

Philipp V. Panitz, Markus Olbrich, Erich Barke, Jürgen Koehl

Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

Incremental Fault Emulation.

Jan Torben Weinkopf, Klaus Harbich, Erich Barke

Proceedings of the FPL 2007, 2007

Range Arithmetics to Speed up Reachability Analysis of Analog Systems.

Darius Grabowski, Markus Olbrich, Christoph Grimm, Erich Barke

Proceedings of the Forum on specification and Design Languages, 2007

CMCal: an accurate analytical approach for the analysis of process variations with non-gaussian parameters and nonlinear functions.

Min Zhang, Markus Olbrich, David Seider, Martin Frerichs, Harald Kinzelbach, Erich Barke

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Efficient Modeling Techniques for Dynamic Voltage Drop Analysis.

Hedi Harizi, Robert HauBler, Markus Olbrich, Erich Barke

Proceedings of the 44th Design Automation Conference, 2007

2006

Ansätze zur Verbesserung der Simulationsperformance automatisch generierter analoger Verhaltensmodelle.

Daniel Platte, Shangjing Jing, Ralf Sommer, Erich Barke

Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2006

Vermeidung fehlerhafter Verifikations-Ergebnisse beim Äquivalenz-Vergleich nichtlinearer analoger Schaltungen.

Ralf Klausen, Lars Hedrich, Erich Barke

Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2006

Ein Verfahren zur effizienten Analyse von Schaltungen mit Parametervarianzen.

Darius Grabowski, Christoph Grimm, Erich Barke

Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2006

Semi-symbolic modeling and simulation of circuits and systems.

Darius Grabowski, Christoph Grimm, Erich Barke

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Parsifal: A Generic and Configurable Fault Emulation Environment with Non-Classical Fault Models.

Jan Torben Weinkopf, Klaus Harbich, Erich Barke

Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

Using Sequential Equations to Improve Efficiency and Robustness.

Daniel Platte, Shangjing Jing, Ralf Sommer, Erich Barke

Proceedings of the Forum on specification and Design Languages, 2006

2005

Time Constrained Verification of Analog Circuits using Model-Checking Algorithms.

Darius Grabowski, Daniel Platte, Lars Hedrich, Erich Barke

Proceedings of the First Workshop on Formal Verification of Analog Circuits, 2005

Routing of analog busses with parasitic symmetry.

Lars A. Schreiner, Markus Olbrich, Erich Barke, Volker Meyer zu Bexten

Proceedings of the 2005 International Symposium on Physical Design, 2005

2004

Wirelength Reduction Using 3-D Physical Design.

Idris Kaya, Silke Salewski, Markus Olbrich, Erich Barke

Proceedings of the Integrated Circuit and System Design, 2004

Placement Using a Localization Probability Model (LPM).

Markus Olbrich, Erich Barke

Proceedings of the 2004 Design, 2004

Hierarchical Automatic Behavioral Model Generation of Nonlinear Analog Circuits Based on Nonlinear Symbolic Techniques.

Lutz Näthke, Volodymyr Burkhay, Lars Hedrich, Erich Barke

Proceedings of the 2004 Design, 2004

2003

Substrate Modeling and Noise Reduction in Mixed-Signal Circuits.

Andreas Hermann, Markus Olbrich, Erich Barke

Proceedings of the IFIP VLSI-SoC 2003, 2003

Placing substrate contacts into mixed-signal circuits controlling circuit performance.

Andreas Hermann, Markus Olbrich, Erich Barke

Proceedings of the IEEE Custom Integrated Circuits Conference, 2003

2002

An Upper Bound for 3D Slicing Floorplans.

Silke Salewski, Erich Barke

Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

Analog circuit sizing based on formal methods using affine arithmetic.

Andreas C. Lemke, Lars Hedrich, Erich Barke

Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

Parameter Controlled Automatic Symbolic Analysis of Nonlinear Analog Circuits.

Ralf Popp, Joerg Oehmen, Lars Hedrich, Erich Barke

Proceedings of the 2002 Design, 2002

An Approach to Model Checking for Nonlinear Analog Systems.

Walter Hartong, Lars Hedrich, Erich Barke

Proceedings of the 2002 Design, 2002

A Direct Mapping System for Datapath Module and FSM Implementation into LUT-Based FPGAs .

Joerg Abke, Erich Barke

Proceedings of the 2002 Design, 2002

Model checking algorithms for analog verification.

Walter Hartong, Lars Hedrich, Erich Barke

Proceedings of the 39th Design Automation Conference, 2002

On Discrete Modeling and Model Checking for Nonlinear Analog Systems.

Walter Hartong, Lars Hedrich, Erich Barke

Proceedings of the Computer Aided Verification, 14th International Conference, 2002

2001

CHIPDESIGN - A Novel Project-oriented Microelectronics Course.

Mark Bernd Kulaczewski, Stefan Zimmerman, Erich Barke, Peter Pirsch

Proceedings of the 2001 International Conference on Microelectronics Systems Education, 2001

PuMA++: From Behavioral Specification to Multi-FPGA-Prototype.

Klaus Harbich, Erich Barke

Proceedings of the Field-Programmable Logic and Applications, 2001

A New Placement Method for Direct Mapping into LUT-Based FPGAs.

Joerg Abke, Erich Barke

Proceedings of the Field-Programmable Logic and Applications, 2001

An improved hierarchical classification algorithm for structural analysis of integrated circuits.

Markus Olbrich, Achim Rein, Erich Barke

Proceedings of the Conference on Design, Automation and Test in Europe, 2001

Architecture driven partitioning.

Joachim Küter, Erich Barke

Proceedings of the Conference on Design, Automation and Test in Europe, 2001

2000

PARCOURS - Substrate Crosstalk Analysis for Complex Mixed-Signal-Circuits.

Andreas Herrmann, Erich Barke, Mathias Silvant, Jürgen Schlöffel

Proceedings of the Integrated Circuit Design, 2000

CoMGen: Direct Mapping of Arbitrary Components into LUT-Based FPGAs.

Joerg Abke, Erich Barke

Proceedings of the Field-Programmable Logic and Applications, 2000

Static Timing Analysis Taking Crosstalk into Account.

Matthias Ringe, Thomas Lindenkreuz, Erich Barke

Proceedings of the 2000 Design, 2000

Single Step Current Driven Routing of Multiterminal Signal Nets for Analog Applications.

Thorsten Adler, Erich Barke

Proceedings of the 2000 Design, 2000

A current driven routing and verification methodology for analog applications.

Thorsten Adler, Hiltrud Brocke, Lars Hedrich, Erich Barke

Proceedings of the 37th Conference on Design Automation, 2000

1999

A Case Study: Logic Emulation - Pitfalls and Solutions.

Klaus Harbich, Jörn Stohmann, Erich Barke, Ludwig Schwoerer

Proceedings of the Tenth IEEE International Workshop on Rapid System Prototyping (RSP 1999), 1999

A Universal Module Generator for LUT-Based FPGAs.

Joerg Abke, Erich Barke, Jörn Stohmann

Proceedings of the Tenth IEEE International Workshop on Rapid System Prototyping (RSP 1999), 1999

An extended bipolar transistor model for substrate crosstalk analysis.

M. Klemme, Erich Barke

Proceedings of the IEEE 1999 Custom Integrated Circuits Conference, 1999

1998

An Optimized Design Flow for Fast FPGA-Based Rapid Prototyping.

Jörn Stohmann, Klaus Harbich, Markus Olbrich, Erich Barke

Proceedings of the Field-Programmable Logic and Applications, 1998

Path Verification Using Boolean Satisfiability.

Matthias Ringe, Thomas Lindenkreuz, Erich Barke

Proceedings of the 1998 Design, 1998

A Formal Approach to Verification of Linear Analog Circuits with Parameter Tolerances.

Lars Hedrich, Erich Barke

Proceedings of the 1998 Design, 1998

Real Time Fault Injection Using Logic Emulators.

Reza Sedaghat-Maman, Erich Barke

Proceedings of the ASP-DAC '98, 1998

1997

A new approach to fault emulation.

Reza Sedaghat-Maman, Erich Barke

Proceedings of the Proceedings 8th IEEE International Workshop on Rapid System Prototyping: Shortening the Path from Specification to Prototype, 1997

A Universal Pezaris Array Multiplier Generator for SRAM-Based FPGAs.

Jörn Stohmann, Erich Barke

Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

Design driven partitioning.

Dirk Behrens, Erich Barke, Robert Tolkiehn

Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997

1996

Hierarchical partitioning.

Dirk Behrens, Klaus Harbich, Erich Barke

Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

A Universal CLA Adder Generator for SRAM-Based FPGAs.

Jörn Stohmann, Erich Barke

Proceedings of the Field-Programmable Logic, 1996

PALACE: A Parallel and Hierarchical Layout Analyzer and Circuit Extractor.

Frank Scherber, Erich Barke, Wolfgang Meier

Proceedings of the 1996 European Design and Test Conference, 1996

Equation-Based Behavioral Model Generation for Nonlinear Analog Circuits.

Carsten Borchers, Lars Hedrich, Erich Barke

Proceedings of the 33st Conference on Design Automation, 1996

1995

A formal approach to nonlinear analog circuit verification.

Lars Hedrich, Erich Barke

Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

1988

Line-to-ground capacitance calculation for VLSI: a comparison.

Erich Barke

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988

1985

FERKEL: Technologieunabhängiges direktivengesteuertes Programmsystem zur Entwurfsregelnprüfung.

Erich Barke

Angew. Inform., 1985

Resistance calculation from mask artwork data by finite element method.

Erich Barke

Proceedings of the 22nd ACM/IEEE conference on Design automation, 1985

1984

A Network Comparison Algorithm for Layout Verification of Integrated Circuits.

Erich Barke

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1984

Figurenorientierte boolesche Maskenoperationen für die Layout-Prüfung integrierter Schaltungen / Polygon-based boolean mask operations to be used in IC design rule checking.

Erich Barke

Elektron. Rechenanlagen, 1984

A technology independent block extraction algorithm.

F. Luellau, T. Hoepken, Erich Barke

Proceedings of the 21st Design Automation Conference, 1984

1983

A layout verification system for analog bipolar integrated circuits.

Erich Barke

Proceedings of the 20th Design Automation Conference, 1983