Markus Bühler

According to our database, Markus Bühler authored at least 14 papers between 1998 and 2017.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2017

Strategies for Forward Modelling of Infrared Radiative Transfer on GPUs.

Paul F. Baumeister, B. Rombach, Thorsten Hater, Sabine Griessbach, L. Hoffmann, Markus Bühler, Dirk Pleiter

Proceedings of the Parallel Computing is Everywhere, 2017

2016

Exploring Energy Efficiency for GPU-Accelerated POWER Servers.

Thorsten Hater, Benedikt Anlauf, Paul F. Baumeister, Markus Bühler, Jiri Kraus, Dirk Pleiter

Proceedings of the High Performance Computing, 2016

Performance of the 3D Combustion Simulation Code RECOM®-AIOLOS on IBM® POWER8® Architecture.

Alexander Berreth, Benedetto Risio, Markus Bühler, Benedikt Anlauf, Pascal Vezolle

Proceedings of the High Performance Computing, 2016

Addressing Materials Science Challenges Using GPU-accelerated POWER8 Nodes.

Paul F. Baumeister, Marcel Bornemann, Markus Bühler, Thorsten Hater, Benjamin Krill, Dirk Pleiter, Rudolf Zeller

Proceedings of the Euro-Par 2016: Parallel Processing, 2016

2011

Design methodology for the IBM POWER7 microprocessor.

Joshua Friedrich, Ruchir Puri, Uwe Brandt, Markus Bühler, Jack DiLullo, Jeremy Hopkins, Mozammel Hossain, Michael A. Kazda, Joachim Keinert, Zahi M. Kurzum, Douglass Lamb, Alice Lee, Frank Musante, Jens Noack, Peter J. Osler, Stephen D. Posluszny, Haifeng Qian, Shyam Ramji, Vasant B. Rao, Lakshmi N. Reddy, Haoxing Ren, Thomas E. Rosser, Benjamin R. Russell, Cliff C. N. Sze, Gustavo E. Téllez

IBM J. Res. Dev., 2011

A gate sizing method for glitch power reduction.

Lei Wang, Markus Olbrich, Erich Barke, Thomas Büchner, Markus Bühler, Philipp V. Panitz

Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011

A theoretical probabilistic simulation framework for dynamic power estimation.

Lei Wang, Markus Olbrich, Erich Barke, Thomas Büchner, Markus Bühler, Philipp V. Panitz

Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

2009

Fast dynamic power estimation considering glitch filtering.

Lei Wang, Markus Olbrich, Erich Barke, Thomas Büchner, Markus Bühler

Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

2008

Considering possible opens in non-tree topology wire delay calculation.

Philipp V. Panitz, Markus Olbrich, Erich Barke, Markus Bühler, Jürgen Koehl

Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

2006

Yield Improvement by Local Wiring Redundancy.

Jeanne Bickford, Jason Hibbeler, Markus Bühler, Jürgen Koehl, Dirk Müller, Sven Peyer, Christian Schulte

Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

DFM/DFY design for manufacturability and yield - influence of process variations in digital, analog and mixed-signal circuit design.

Markus Bühler, Jürgen Koehl, Jeanne Bickford, Jason Hibbeler, Ulf Schlichtmann, Ralf Sommer, Michael Pronath, Andreas Ripp

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

1999

Efficient Switching Activity Simulation under a Real Delay Model Using a Bitparallel Approach.

Markus Bühler, Matthias Papesch, K. Kapp, Utz G. Baitinger

Proceedings of the 1999 Design, 1999

1998

Switching Activity Analysis Using a Set Theoretical Approach.

Markus Bühler, D. Dallmann, Utz G. Baitinger

Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 1998

TESA: Timeparallel Estimation of Switching Activity under a real delay model.

K. Kapp, Markus Bühler, D. Dallmann, Utz G. Baitinger

Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998