Piao Zhe

According to our database, Piao Zhe authored at least 4 papers between 2008 and 2011.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2011

Power Supply Voltage Dependence of Within-Die Delay Variation of Regular Manual Layout and Irregular Place-and-Route Layout.

Tadashi Yasufuku, Yasumi Nakamura, Piao Zhe, Makoto Takamiya, Takayasu Sakurai

IEICE Trans. Electron., 2011

2010

Difficulty of Power Supply Voltage Scaling in Large Scale Subthreshold Logic Circuits.

Tadashi Yasufuku, Taro Niiyama, Piao Zhe, Koichi Ishida, Masami Murakata, Makoto Takamiya, Takayasu Sakurai

IEICE Trans. Electron., 2010

2008

Dependence of Minimum Operating Voltage (VDDmin) on Block Size of 90-nm CMOS Ring Oscillators and its Implications in Low Power DFM.

Taro Niiyama, Piao Zhe, Koichi Ishida, Masami Murakata, Makoto Takamiya, Takayasu Sakurai

Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Increasing minimum operating voltage (V_DDmin) with number of CMOS logic gates and experimental verification with up to 1Mega-stage ring oscillators.

Taro Niiyama, Piao Zhe, Koichi Ishida, Masami Murakata, Makoto Takamiya, Takayasu Sakurai

Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008