Masami Murakata

According to our database1, Masami Murakata authored at least 13 papers between 1995 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2020
An Architectural Study for Inference Coprocessor Core at the Edge in IoT Sensing.
Proceedings of the 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2020

2010
Difficulty of Power Supply Voltage Scaling in Large Scale Subthreshold Logic Circuits.
IEICE Trans. Electron., 2010

2008
Dependence of Minimum Operating Voltage (VDDmin) on Block Size of 90-nm CMOS Ring Oscillators and its Implications in Low Power DFM.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Increasing minimum operating voltage (V<sub>DDmin</sub>) with number of CMOS logic gates and experimental verification with up to 1Mega-stage ring oscillators.
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008

Experimental assessment of logic circuit performance variability with regular fabrics at 90nm technology node.
Proceedings of the ESSCIRC 2008, 2008

2006
A 63-mW H.264/MPEG-4 audio/visual codec LSI with module-wise dynamic Voltage/frequency scaling.
IEEE J. Solid State Circuits, 2006

Module-Wise Dynamic Voltage and Frequency Scaling for a 90 nm H.264/MPEG-4 Codec LSI.
IEICE Trans. Electron., 2006

1998
A DRAM module generator with an expandable cell array scheme.
Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, 1998

A Clock-Gating Method for Low-Power LSI Design.
Proceedings of the ASP-DAC '98, 1998

1997
Layout Driven Re-synthesis for Low Power Consumption LSIs.
Proceedings of the 34st Conference on Design Automation, 1997

1996
Switching activity analysis for sequential circuits using Boolean approximation method.
Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996

Physical design CAD in deep sub-micron era.
Proceedings of the conference on European design automation, 1996

1995
Fanout-tree restructuring algorithm for post-placement timing optimization.
Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995


  Loading...