Tadashi Yasufuku
According to our database1,
Tadashi Yasufuku
authored at least 18 papers
between 2009 and 2018.
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Bibliography
2018
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
2013
Minimizing Energy of Integer Unit by Higher Voltage Flip-Flop: V<sub>DDmin</sub>-Aware Dual Supply Voltage Technique.
IEEE Trans. Very Large Scale Integr. Syst., 2013
2012
Large Within-Die Gate Delay Variations in Sub-Threshold Logic Circuits at Low Temperature.
IEEE Trans. Circuits Syst. II Express Briefs, 2012
13% Power reduction in 16b integer unit in 40nm CMOS by adaptive power supply voltage control with parity-based error prediction and detection (PEPD) and fully integrated digital LDO.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
24% Power reduction by post-fabrication dual supply voltage control of 64 voltage domains in V<sub>DDmin</sub> limited ultra low voltage logic circuits.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012
2011
1.8 V Low-Transient-Energy Adaptive Program-Voltage Generator Based on Boost Converter for 3D-Integrated NAND Flash SSD.
IEEE J. Solid State Circuits, 2011
Power Supply Voltage Dependence of Within-Die Delay Variation of Regular Manual Layout and Irregular Place-and-Route Layout.
IEICE Trans. Electron., 2011
Investigation of determinant factors of minimum operating voltage of logic gates in 65-nm CMOS.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011
12.7-times energy efficiency increase of 16-bit integer unit by power supply voltage (V<sub>DD</sub>) scaling from 1.2v to 310mv enabled by contention-less flip-flops (CLFF) and separated V<sub>DD</sub> between flip-flops and combinational logics.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011
12% Power reduction by within-functional-block fine-grained adaptive dual supply voltage control in logic circuits with 42 voltage domains.
Proceedings of the 37th European Solid-State Circuits Conference, 2011
A closed-form expression for estimating minimum operating voltage (V<sub>DDmin</sub>) of CMOS logic gates.
Proceedings of the 48th Design Automation Conference, 2011
2010
Stretchable EMI Measurement Sheet With 8 ˟ 8 Coil Array, 2 V Organic CMOS Decoder, and 0.18 μ m Silicon CMOS LSIs for Electric and Magnetic Field Detection.
IEEE J. Solid State Circuits, 2010
Difficulty of Power Supply Voltage Scaling in Large Scale Subthreshold Logic Circuits.
IEICE Trans. Electron., 2010
Inductor and TSV Design of 20-V Boost Converter for Low Power 3D Solid State Drive with NAND Flash Memories.
IEICE Trans. Electron., 2010
2009
A 1.8V 30nJ adaptive program-voltage (20V) generator for 3D-integrated NAND flash SSD.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
A stretchable EMI measurement sheet with 8×8 coil array, 2V organic CMOS decoder, and -70dBm EMI detection circuits in 0.18¼m CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
Inductor design of 20-V boost converter for low power 3D solid state drive with NAND flash memories.
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009
Effect of resistance of TSV's on performance of boost converter for low power 3D SSD with NAND flash memories.
Proceedings of the IEEE International Conference on 3D System Integration, 2009