Pierre Guillemin

According to our database1, Pierre Guillemin authored at least 8 papers between 2005 and 2010.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

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Bibliography

2010
Block-Level Added Redundancy Explicit Authentication for Parallelized Encryption and Integrity Checking of Processor-Memory Transactions.
Trans. Comput. Sci., 2010

2009
SecBus: Operating System controlled hierarchical page-based memory bus protection.
Proceedings of the Design, Automation and Test in Europe, 2009

2007
TEC-Tree: A Low-Cost, Parallelizable Tree for Efficient Defense Against Memory Replay Attacks.
Proceedings of the Cryptographic Hardware and Embedded Systems, 2007

2006
Efficient Combination of Data Encryption and Integrity Checking for Embedded Systems.
Proceedings of the 2nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2006

A Comparison of Two Approaches Providing Data Encryption and Authentication on a Processor Memory Bus.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

PE-ICE: Parallelized Encryption and Integrity Checking Engine.
Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006

A parallelized way to provide data encryption and integrity checking on a processor-memory bus.
Proceedings of the 43rd Design Automation Conference, 2006

2005
Hardware Engines for Bus Encryption: A Survey of Existing Techniques.
Proceedings of the 2005 Design, 2005


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