Pierre-Henri Horrein

Orcid: 0000-0002-9714-7871

According to our database1, Pierre-Henri Horrein authored at least 19 papers between 2009 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2022
Toward Agile Hardware Designs With Chisel: A Network Use Case.
IEEE Des. Test, 2022

2020
(System)Verilog to Chisel Translation for Faster Hardware Design.
Proceedings of the International Workshop on Rapid System Prototyping, 2020

2018
Spatio-Temporal Interpolation of Cloudy SST Fields Using Conditional Analog Data Assimilation.
Remote. Sens., 2018

2017
Large-Scale Memory of Sequences Using Binary Sparse Neural Networks on GPU.
Proceedings of the 2017 International Conference on High Performance Computing & Simulation, 2017

Open-source flexible packet parser for high data rate agile network probe.
Proceedings of the 2017 IEEE Conference on Communications and Network Security, 2017

Combining FPGAs and processors for high-throughput forensics IEEE CNS 17 poster.
Proceedings of the 2017 IEEE Conference on Communications and Network Security, 2017

2016
Massively parallel implementation of sparse message retrieval algorithms in Clustered Clique Networks.
Proceedings of the International Conference on High Performance Computing & Simulation, 2016

Ouessant: Microcontroller approach for flexible accelerator integration and control in System-on-Chip.
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

AutoReloc: Automated Design Flow for Bitstream Relocation on Xilinx FPGAs.
Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016

Ouessant: Flexible integration of dedicated coprocessors in Systems on Chip.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
Caasper: providing accessible FPGA-acceleration over the network.
Proceedings of the 2015 International Symposium on Rapid System Prototyping, 2015

2014
UWB-IR digital baseband architecture for IEEE 802.15.6 wireless BAN.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

Energy-efficient FPGA implementation for binomial option pricing using OpenCL.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
An environment for (re)configuration and execution management of heterogeneous flexible radio platforms.
Microprocess. Microsystems, 2013

2012
Architectures logicielles pour la radio flexible : intégration d'unités de calcul hétérogènes. (Software design for flexible radio : integration of heterogeneous computing units).
PhD thesis, 2012

Integration of GPU Computing in a Software Radio Environment.
J. Signal Process. Syst., 2012

HCM: An abstraction layer for seamless programming of DPR FPGA.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

2011
An Environment for (re)configuration and Execution Managenment of Flexible Radio Platforms.
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

2009
A MPSoC Prototyping Platform for Flexible Radio Applications.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009


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