Frédéric Pétrot

According to our database1, Frédéric Pétrot authored at least 119 papers between 1991 and 2019.

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2019
Efficient Decompression of Binary Encoded Balanced Ternary Sequences.
IEEE Trans. VLSI Syst., 2019

Loop aware CFG matching strategy for accurate performance estimation in IR-level native simulation.
Integration, 2019

Multi-Triggered Embedded Software Code Generation for Electrical Metering and Protection Applications.
Proceedings of the 30th International Workshop on Rapid System Prototyping, 2019

2018
High-Efficiency Convolutional Ternary Neural Networks with Custom Adder Trees and Weight Compression.
TRETS, 2018

Message-Oriented Devices on FPGAs.
Proceedings of the 2018 International Symposium on Rapid System Prototyping, 2018

Overview of the state of the art in embedded machine learning.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

A mapping approach between IR and binary CFGs dealing with aggressive compiler optimizations for performance estimation.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

Dynamic Coherent Cluster: A Scalable Sharing Set Management Approach.
Proceedings of the 29th IEEE International Conference on Application-specific Systems, 2018

2017
Multiprocessor System-on-Chip Prototyping Using Dynamic Binary Translation.
Proceedings of the Handbook of Hardware/Software Codesign., 2017

Efficient and Versatile FPGA Acceleration of Support Counting for Stream Mining of Sequences and Frequent Itemsets.
TRETS, 2017

Detecting Software Cache Coherence Violations in MPSoC Using Traces Captured on Virtual Platforms.
ACM Trans. Embedded Comput. Syst., 2017

Dynamic Binary Translation of VLIW Codes on Scalar Architectures.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2017

A 4 × 4 × 2 Homogeneous Scalable 3D Network-on-Chip Circuit With 326 MFlit/s 0.66 pJ/b Robust and Fault Tolerant Asynchronous 3D Links.
J. Solid-State Circuits, 2017

Trace-driven exploration of sharing set management strategies for cache coherence in manycores.
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017

A Meta-Routing Method to Create Multiple Virtual Logical Networks on a Single Hardware NoC.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Ternary neural networks for resource-efficient AI applications.
Proceedings of the 2017 International Joint Conference on Neural Networks, 2017

Scalable high-performance architecture for convolutional ternary neural networks on FPGA.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

Optimizing Memory Access Performance Using Hardware Assisted Virtualization in Retargetable Dynamic Binary Translation.
Proceedings of the Euromicro Conference on Digital System Design, 2017

A Distributed NUCA Architecture Using an Efficient NoC Multicasting Support.
Proceedings of the Euromicro Conference on Digital System Design, 2017

Modeling instruction cache and instruction buffer for performance estimation of VLIW architectures using native simulation.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

IR-level annotation strategy dealing with aggressive loop optimizations for performance estimation in native simulation: work-in-progress.
Proceedings of the Twelfth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Companion, 2017

Loop aware IR-level annotation framework for performance estimation in native simulation.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

A Method for Fast Evaluation of Sharing Set Management Strategies in Cache Coherence Protocols.
Proceedings of the Architecture of Computing Systems - ARCS 2017, 2017

2016
Deterministic reversible MPSoC debugger based on virtual platform execution traces.
Design Autom. for Emb. Sys., 2016

Facing ADAS validation complexity with usage oriented testing.
CoRR, 2016

Ternary Neural Networks for Resource-Efficient AI Applications.
CoRR, 2016

Simulation driven insertion of data prefetching instructions for early software-on-SoC optimization.
Proceedings of the 2016 International Symposium on Rapid System Prototyping, 2016

8.1 A 4×4×2 homogeneous scalable 3D network-on-chip circuit with 326MFlit/s 0.66pJ/b robust and fault-tolerant asynchronous 3D links.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

Virtual prototyping of floating point units.
Proceedings of the 2016 Workshop on Rapid Simulation and Performance Evaluation, 2016

2015
Simulation native basée sur le support matériel à la virtualisation cas des systèmes many-cœurs spécifiques.
Technique et Science Informatiques, 2015

Collecting traces in dynamic binary translation based virtual prototyping platforms.
Proceedings of the 2015 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, 2015

Fast and accurate branch predictor simulation.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
Assignment of Vertical-Links to Routers in Vertically-Partially-Connected 3-D-NoCs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2014

Device driver generation targeting multiple operating systems using a model-driven methodology.
Proceedings of the 25nd IEEE International Symposium on Rapid System Prototyping, 2014

System on chip project: Integration of a Motion-JPEG video decoder.
Proceedings of the 10th European Workshop on Microelectronics Education (EWME), 2014

Scalability bottlenecks discovery in MPSoC platforms using data mining on simulation traces.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
An Iterative Computational Technique for Performance Evaluation of Networks-on-Chip.
IEEE Trans. Computers, 2013

Elevator-First: A Deadlock-Free Distributed Routing Algorithm for Vertically Partially Connected 3D-NoCs.
IEEE Trans. Computers, 2013

An environment for (re)configuration and execution management of heterogeneous flexible radio platforms.
Microprocessors and Microsystems - Embedded Hardware Design, 2013

Design of a medium voltage protection device using system simulation approaches: a case study.
IJES, 2013

Automated generation of efficient instruction decoders for instruction set simulators.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

A General Framework for Average-Case Performance Analysis of Shared Resources.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

A system-level overview and comparison of three High-Speed Serial Links: USB 3.0, PCI Express 2.0 and LLI 1.0.
Proceedings of the 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2013

Data mining MPSoC simulation traces to identify concurrent memory access patterns.
Proceedings of the Design, Automation and Test in Europe, 2013

Native simulation of complex VLIW instruction sets using static binary translation and Hardware-Assisted Virtualization.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012
Integration of GPU Computing in a Software Radio Environment.
Signal Processing Systems, 2012

Native Simulation of MPSoC Using Hardware-Assisted Virtualization.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2012

Automatic congestion detection in MPSoC programs using data mining on simulation traces.
Proceedings of the 23rd IEEE International Symposium on Rapid System Prototyping, 2012

A 3D-NoC Router Implementation Exploiting Vertically-Partially-Connected Topologies.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

Accurate on-chip router area modeling with Kriging methodology.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

HCM: An abstraction layer for seamless programming of DPR FPGA.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

Multi-device Driver Synthesis Flow for Heterogeneous Hierarchical Systems.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

Cost-efficient buffer sizing in shared-memory 3D-MPSoCs using wide I/O interfaces.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Fast simulation of systems embedding VLIW processors.
Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012

2011
Asynchronous 3D-NoCs Making Use of Serialized Vertical Links.
Proceedings of the 3D Integration for NoC-based SoC Architectures, 2011

Systèmes de mémoire transactionnelle pour les architectures à base de NoC Conception, implémentation et comparaison de deux politiques.
Technique et Science Informatiques, 2011

On MPSoC Software Execution at the Transaction Level.
IEEE Design & Test of Computers, 2011

A non intrusive simulation-based trace system to analyse Multiprocessor Systems-on-Chip software.
Proceedings of the 22nd IEEE International Symposium on Rapid System Prototyping, 2011

Me3D: A model-driven methodology expediting embedded device driver development.
Proceedings of the 22nd IEEE International Symposium on Rapid System Prototyping, 2011

Spidergon STNoC design flow.
Proceedings of the NOCS 2011, 2011

Physical Implementation of an Asynchronous 3D-NoC Router Using Serial Vertical Links.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

An Environment for (re)configuration and Execution Managenment of Flexible Radio Platforms.
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

Speeding-up SIMD instructions dynamic binary translation in embedded processor simulation.
Proceedings of the Design, Automation and Test in Europe, 2011

Handling dynamic frequency changes in statically scheduled cycle-accurate simulation.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

Using Amdahl's Law for Performance Analysis of Many-Core SoC Architectures Based on Functionally Asymmetric Processors.
Proceedings of the Architecture of Computing Systems - ARCS 2011, 2011

2010
Hardware/software support for adaptive work-stealing in on-chip multiprocessor.
Journal of Systems Architecture - Embedded Systems Design, 2010

Lightweight Transactional Memory systems for NoCs based architectures: Design, implementation and comparison of two policies.
J. Parallel Distrib. Comput., 2010

Evaluation of the implementation cost of cache coherence protocols using omniscient actions.
Design Autom. for Emb. Sys., 2010

Improving the tests coverage of a medium voltage protection device using system simulation approaches.
Proceedings of the IEEE Fifth International Symposium on Industrial Embedded Systems, 2010

Design environment for the support of configurable Network Interfaces in NoC-based platforms.
Proceedings of the 2010 International Conference on Embedded Computer Systems: Architectures, 2010

A flexible hybrid simulation platform targeting multiple configurable processors SoC.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009
Modelling and architecture exploration of a medium voltage protection device.
Proceedings of the IEEE Fourth International Symposium on Industrial Embedded Systems, 2009

Synthesis of Communication Mechanisms for Multi-tile Systems Based on Heterogeneous Multi-processor System-On-Chips.
Proceedings of the Twentienth IEEE/IFIP International Symposium on Rapid System Prototyping, 2009

Practical Design Space Exploration of an H264 Decoder for Handheld Devices Using a Virtual Platform.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009

Abstract Description of System Application and Hardware Architecture for Hardware/Software Code Generation.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

A MPSoC Prototyping Platform for Flexible Radio Applications.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

Adaptive Dynamic Voltage and Frequency Scaling Algorithm for Symmetric Multiprocessor Architecture.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

Extending IP-XACT to support an MDE based approach for SoC design.
Proceedings of the Design, Automation and Test in Europe, 2009

Using binary translation in event driven simulation for fast and flexible MPSoC simulation.
Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, 2009

Native MPSoC co-simulation environment for software performance estimation.
Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, 2009

Novel task migration framework on configurable heterogeneous MPSoC platforms.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

Automatic instrumentation of embedded software for high level hardware/software co-simulation.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

A System Framework for the Design of Embedded Software Targeting Heterogeneous Multi-core SoCs.
Proceedings of the 20th IEEE International Conference on Application-Specific Systems, 2009

2008
Estimation et optimisation de la consommation dans les SoC utilisant la simulation précise au cycle.
Technique et Science Informatiques, 2008

Parallel Programming of Multi-processor SoC: A HW-SW Interface Perspective.
International Journal of Parallel Programming, 2008

MPSoC Communication Architecture Exploration Using an Abstraction Refinement Method.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

An intermediate format for automatic generation of MPSoC virtual prototypes.
Proceedings of the 2008 International Conference on Embedded Computer Systems: Architectures, 2008

Configurable Heterogeneous MPSoC Architecture Exploration Using Abstraction Levels.
Proceedings of the 19th IEEE/IFIP International Symposium on Rapid System Prototyping: RSP 2009, 2008

Multi-CPU/FPGA Platform Based Heterogeneous Multiprocessor Prototyping: New Challenges for Embedded Software Designers.
Proceedings of the 19th IEEE/IFIP International Symposium on Rapid System Prototyping: RSP 2009, 2008

Large Scale On-Chip Networks : An Accurate Multi-FPGA Emulation Platform.
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

Comparison of memory write policies for NoC based Multicore Cache Coherent Systems.
Proceedings of the Design, Automation and Test in Europe, 2008

Efficient Implementation of Native Software Simulation for MPSoC.
Proceedings of the Design, Automation and Test in Europe, 2008

2007
On SPARC LEON-2 ISA Extensions Experiments for MPEG Encoding Acceleration.
VLSI Design, 2007

Prototyping Multiprocessor System-on-Chip Applications: A Platform-Based Approach.
IEEE Distributed Systems Online, 2007

Scalable Multi-FPGA Platform for Networks-On-Chip Emulation.
Proceedings of the IEEE International Conference on Application-Specific Systems, 2007

2006
Fast Prototyping of POSIX Based Applications on a Multiprocessor SoC Architecture: "Hardware-Dependent Software Oriented Approach".
Proceedings of the 17th IEEE International Workshop on Rapid System Prototyping (RSP 2006), 2006

Service Based Component Design Approach for Flexible Hardware/Software Interface Modeling.
Proceedings of the 17th IEEE International Workshop on Rapid System Prototyping (RSP 2006), 2006

MP-SoC Architecture for an Obstacle Detection Application in Pre-Crash Situation.
Proceedings of the 2nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2006

On Cache Coherency and Memory Consistency Issues in NoC Based Shared Memory Multiprocessor SoC Architectures.
Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006

Programming models and HW-SW interfaces abstraction for multi-processor SoC.
Proceedings of the 43rd Design Automation Conference, 2006

2005
Platform-based design from parallel C specifications.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2005

A unified HW/SW interface model to remove discontinuities between HW and SW design.
Proceedings of the EMSOFT 2005, 2005

2004
Intégration sur plate-forme matérielle/logicielle de spécifications 'C' parallèles.
Annales des Télécommunications, 2004

Modular On-chip Multiprocessor for Routing Applications.
Proceedings of the Euro-Par 2004 Parallel Processing, 2004

2003
Retiming Finite State Machines to Control Hardened Data-Paths.
Proceedings of the 16th Annual Symposium on Integrated Circuits and Systems Design, 2003

Lightweight Implementation of the POSIX Threads API for an On-Chip MIPS Multiprocessor with VCI Interconnect.
Proceedings of the 2003 Design, 2003

Lightweight Implementation of the POSIX Threads API for an On-Chip MIPS Multiprocessor with VCI Interconnect.
Proceedings of the Embedded Software for SoC, 2003

2001
A Tool Box to Map System Level Communications on HW/SW Architectures.
Proceedings of the 12th IEEE International Workshop on Rapid System Prototyping (RSP 2001), 2001

A practical tool box for system level communication synthesis.
Proceedings of the Ninth International Symposium on Hardware/Software Codesign, 2001

2000
A generic programmable arbiter with default master grant.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

COSY communication IP's.
Proceedings of the 37th Conference on Design Automation, 2000

1999
Formal Analysis of Single WAIT VHDL processes for Semantic Based Synthesis.
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

1998
Formal Extraction of Memorizing Elements for Sequential VHDL Synthesis.
Proceedings of the 24th EUROMICRO '98 Conference, 1998

Efficient Combinational Loops Handling for Cycle Precise Simulation of System on a Chip.
Proceedings of the 24th EUROMICRO '98 Conference, 1998

1997
Cycle precise core based hardware/software system simulation with predictable event propagation.
Proceedings of the 23rd EUROMICRO Conference '97, 1997

A Simulation Environment for Core Based Embedded Systems.
Proceedings of the Proceedings 30st Annual Simulation Symposium (SS '97), April 7-9, 1997, 1997

1995
A High Performance Modular Embedded ROM Architecture.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

1994
Using C to write portable CMOS VLSI module generators.
Proceedings of the Proceedings EURO-DAC'94, 1994

1991
GENVIEW: a portable source-level debugger for macrocell generators.
Proceedings of the conference on European design automation, 1991


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