Pil-Seon Yoo

According to our database, Pil-Seon Yoo authored at least 3 papers between 2008 and 2014.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2014

19.2 A 93.4mm² 64Gb MLC NAND-flash memory with 16nm CMOS technology.

Sungdae Choi, Duckju Kim, Sungwook Choi, Byungryul Kim, Sunghyun Jung, Kichang Chun, Namkyeong Kim, Wanseob Lee, Taisik Shin, Hyunjong Jin, Hyunchul Cho, Sunghoon Ahn, Yonghwan Hong, Ingon Yang, Byoungyoung Kim, Pil-Seon Yoo, Youngdon Jung, Jinwoo Lee, Jae-Hyeon Shin, Taeyun Kim, Kunwoo Park, Jinwoong Kim

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2011

A 14b 150 MS/s 140 mW 2.0 mm² 0.13µm CMOS A/D converter for software-defined radio systems.

Hee-Cheol Choi, Pil-Seon Yoo, Gil-Cho Ahn, Seung-Hoon Lee

Int. J. Circuit Theory Appl., 2011

2008

A low offset rail-to-rail 12b 2MS/s 0.18μm CMOS cyclic ADC.

Young-Ju Kim, Hee-Cheol Choi, Pil-Seon Yoo, Dong-Suk Lee, Joong-Ho Choi, Seung-Hoon Lee

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008