Sungdae Choi

According to our database1, Sungdae Choi authored at least 15 papers between 2003 and 2017.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
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PhD thesis 
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Links

On csauthors.net:

Bibliography

2017
EE2: Intelligent machines: Will the technological singularity happen?
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2016
Session 7 overview: Nonvolatile memory solutions.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2014
19.2 A 93.4mm<sup>2</sup> 64Gb MLC NAND-flash memory with 16nm CMOS technology.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2011
High-voltage wordline generator for low-power program operation in NAND flash memories.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

2008
Experimental assessment of logic circuit performance variability with regular fabrics at 90nm technology node.
Proceedings of the ESSCIRC 2008, 2008

2007
A 0.9V 2.6mW Body-Coupled Scalable PHY Transceiver for Body Sensor Applications.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

A Low Power Compression Processor for Body Sensor Network System.
Proceedings of the 4th International Workshop on Wearable and Implantable Body Sensor Networks, 2007

2006
A Low-power Star-topology Body Area Network Controller for Periodic Data Monitoring Around and Inside the Human Body.
Proceedings of the Tenth IEEE International Symposium on Wearable Computers (ISWC 2006), 2006

An Ultra Low-Power Body Sensor Network Control Processor with Centralized Node Control.
Proceedings of the International Symposium on System-on-Chip, 2006

A Multi-Nodes Human Body Communication Sensor Network Control Processor.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

2005
A 0.7-fJ/bit/search 2.2-ns search time hybrid-type TCAM architecture.
IEEE J. Solid State Circuits, 2005

2004
A 210-mW graphics LSI implementing full 3-D pipeline with 264 mtexels/s texturing for mobile multimedia applications.
IEEE J. Solid State Circuits, 2004

A low-power 3D rendering engine with two texture units and 29-Mb embedded DRAM for 3G multimedia terminals.
IEEE J. Solid State Circuits, 2004

A low-power graphics LSI integrating 29Mb embedded DRAM for mobile multimedia applications.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003
A low power 3D rendering engine with two texture units and 29Mb embedded DRAM for 3G multimedia terminals.
Proceedings of the ESSCIRC 2003, 2003


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