Pinalkumar Engineer

According to our database, Pinalkumar Engineer authored at least 12 papers between 2012 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2025

A Template-Based Methodology for Efficient DNNs Inference on FPGA Devices With HW-SW Co-Design.

Swati, Shantanu Banarjee, Pinalkumar Engineer

IEEE Embed. Syst. Lett., August, 2025

Energy-efficient Non-Neural Face Recognition on the Multi-core RISC-V System.

Mitul Sudhirkumar Nagar, Pinalkumar Engineer

Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

2024

High-Speed Energy-Efficient Fixed-Point Signed Multipliers for FPGA-Based DSP Applications.

Mitul Sudhirkumar Nagar, Aditya Mathuriya, Sohan H. Patel, Pinalkumar Engineer

IEEE Embed. Syst. Lett., December, 2024

FPGA-Based High-Speed Energy-Efficient 32-Bit Fixed-Point MAC Architecture for DSP Application in IoT Edge Computing.

Mitul Sudhirkumar Nagar, Sohan H. Patel, Pinalkumar Engineer

J. Circuits Syst. Comput., September, 2024

2023

Parallelizing Non-Neural ML Algorithm for Edge-based Face Recognition on Parallel Ultra-Low Power (PULP) Cluster.

Mitul Sudhirkumar Nagar, Rahul Kumar, Pinalkumar Engineer

Proceedings of the 12th Mediterranean Conference on Embedded Computing, 2023

Memory-efficient Edge-based Non-Neural Face Recognition Algorithm on the Parallel Ultra-Low Power (PULP) Cluster.

Mitul Sudhirkumar Nagar, Sayantan Maiti, Rahul Kumar, Hiren K. Mewada, Pinalkumar Engineer

Proceedings of the 16th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2023

A Memory Efficient Run-time Re-configurable Convolution IP Core for Deep Neural Networks Inference on FPGA Devices.

Swati, Ranajoy Sadhukhan, Mitul Sudhirkumar Nagar, Pinalkumar Engineer

Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2023

Energy-Efficient Acceleration of Deep Learning based Facial Recognition on RISC-V Processor.

Mitul Sudhirkumar Nagar, Vivek Chauhan, Karnav M. Chinchavde, Swati, Sat Patel, Pinalkumar Engineer

Proceedings of the 11th International Conference on Intelligent Systems and Embedded Design, 2023

2020

Scalable implementation of particle filter-based visual object tracking on network-on-chip (NoC).

Pinalkumar Engineer, Rajbabu Velmurugan, Sachin B. Patkar

J. Real Time Image Process., 2020

2015

Framework for Application Mapping over Packet-Switched Network of FPGAs: Case Studies.

Vinay B. Y. Kumar, Pinalkumar Engineer, Mandar Datar, Yatish Turakhia, Saurabh Agarwal, Sanket Diwale, Sachin B. Patkar

CoRR, 2015

Parameterizable FPGA Framework for Particle Filter Based Object Tracking in Video.

Pinalkumar Engineer, Rajbabu Velmurugan, Sachin B. Patkar

Proceedings of the 28th International Conference on VLSI Design, 2015

2012

FPGA Implementation of Particle Filter Based Object Tracking in Video.

Sumeet Agrawal, Pinal Engineer, Rajbabu Velmurugan, Sachin B. Patkar

Proceedings of the International Symposium on Electronic System Design, 2012