Sachin B. Patkar

According to our database, Sachin B. Patkar authored at least 51 papers between 1991 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Experimental Validation of Memristor-Aided Logic Using 1T1R TaOx RRAM Crossbar Array.

Ankit Bende, Simranjeet Singh, Chandan Kumar Jha, Tim Kempen, Felix Cüppers, Christopher Bengel, Andre Zambanini, Dennis Nielinger, Sachin B. Patkar, Rolf Drechsler, Rainer Waser, Farhad Merchant, Vikas Rana

Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

2023

Should We Even Optimize for Execution Energy? Rethinking Mapping for MAGIC Design Style.

Simranjeet Singh, Chandan Kumar Jha, Ankit Bende, Phrangboklang Lyngton Thangkhiew, Vikas Rana, Sachin B. Patkar, Rolf Drechsler, Farhad Merchant

IEEE Embed. Syst. Lett., December, 2023

CLARINET: A quire-enabled RISC-V-based framework for posit arithmetic empiricism.

Niraj N. Sharma, Riya Jain, Mohana Madhumita Pokkuluri, Sachin B. Patkar, Rainer Leupers, Rishiyur S. Nikhil, Farhad Merchant

J. Syst. Archit., February, 2023

MemSPICE: Automated Simulation and Energy Estimation Framework for MAGIC-Based Logic-in-Memory.

Simranjeet Singh, Chandan Kumar Jha, Ankit Bende, Vikas Rana, Sachin B. Patkar, Rolf Drechsler, Farhad Merchant

CoRR, 2023

Integrated Architecture for Neural Networks and Security Primitives using RRAM Crossbar.

Simranjeet Singh, Furqan Zahoor, Gokulnath Rajendran, Vikas Rana, Sachin B. Patkar, Anupam Chattopadhyay, Farhad Merchant

Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023

Finite State Automata Design using 1T1R ReRAM Crossbar.

Simranjeet Singh, Omar Ghazal, Chandan Kumar Jha, Vikas Rana, Rolf Drechsler, Rishad A. Shafik, Alex Yakovlev, Sachin B. Patkar, Farhad Merchant

Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023

Exploring Multi-Valued Logic and its Application in Emerging Post-CMOS Technologies.

Simranjeet Singh, Elmira Moussavi, Christopher Bengel, Sachin B. Patkar, Rainer Waser, Rainer Leupers, Vikas Rana, Vivek Pachauri, Stephan Menzel, Farhad Merchant

Proceedings of the 18th ACM International Symposium on Nanoscale Architectures, 2023

IMBUE: In-Memory Boolean-to-CUrrent Inference ArchitecturE for Tsetlin Machines.

Omar Ghazal, Simranjeet Singh, Tousif Rahman, Shengqi Yu, Yujin Zheng, Domenico Balsamo, Sachin B. Patkar, Farhad Merchant, Fei Xia, Alex Yakovlev, Rishad A. Shafik

Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2023

Hardware Security Primitives Using Passive RRAM Crossbar Array: Novel TRNG and PUF Designs.

Simranjeet Singh, Furqan Zahoor, Gokulnath Rajendran, Sachin B. Patkar, Anupam Chattopadhyay, Farhad Merchant

Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

2022

PA-PUF: A Novel Priority Arbiter PUF.

Simranjeet Singh, Srinivasu Bodapati, Sachin B. Patkar, Rainer Leupers, Anupam Chattopadhyay, Farhad Merchant

Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022

2020

Scalable implementation of particle filter-based visual object tracking on network-on-chip (NoC).

Pinalkumar Engineer, Rajbabu Velmurugan, Sachin B. Patkar

J. Real Time Image Process., 2020

Single Storage Semi-Global Matching for Real Time Depth Processing.

Prathmesh Sawant, Yashwant Temburu, Mandar Datar, Imran Ahmed, Vinayak Shriniwas, Sachin B. Patkar

CoRR, 2020

CLARINET: A RISC-V Based Framework for Posit Arithmetic Empiricism.

Riya Jain, Niraj N. Sharma, Farhad Merchant, Sachin B. Patkar, Rainer Leupers

CoRR, 2020

FPGA-Based Acceleration of LU decomposition for Analog and RF Circuit Simulation.

Yogesh Mahajan, Shashank Obla, Mini K. Namboothiripad, Mandar J. Datar, Niraj N. Sharma, Sachin B. Patkar

Proceedings of the 33rd International Conference on VLSI Design and 19th International Conference on Embedded Systems, 2020

Real time System Implementation for Stereo 3D Mapping and Visual Odometry.

Yashwant Temburu, Mandar Datar, Simranjeet Singh, Vaibhav Malviya, Sachin B. Patkar

Proceedings of the 4th IEEE International Conference on Image Processing, 2020

Accelerated Stereo Vision Using Nvidia Jetson and Intel AVX.

Imran A. Syed, Mandar Datar, Sachin B. Patkar

Proceedings of the Computer Vision and Image Processing - 5th International Conference, 2020

2019

Computational Issues in Construction of 4-D Projective Spaces with Perfect Access Patterns for Higher Primes.

Shreeniwas N. Sapre, Sachin B. Patkar, Supratim Biswas

Proceedings of the Parallel Computing Technologies, 2019

2018

Lightweight Forth Programmable NoCs.

Vinay B. Y. Kumar, Deval Shah, Mandar Datar, Sachin B. Patkar

Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018

2016

Relaxation Based Circuit Simulation Acceleration over CPU-FPGA.

Vinay B. Y. Kumar, Kulshreshth Dhiman, Mandar Datar, Akash Pacharne, H. Narayanan, Sachin B. Patkar

Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

2015

Framework for Application Mapping over Packet-Switched Network of FPGAs: Case Studies.

Vinay B. Y. Kumar, Pinalkumar Engineer, Mandar Datar, Yatish Turakhia, Saurabh Agarwal, Sanket Diwale, Sachin B. Patkar

CoRR, 2015

Parameterizable FPGA Framework for Particle Filter Based Object Tracking in Video.

Pinalkumar Engineer, Rajbabu Velmurugan, Sachin B. Patkar

Proceedings of the 28th International Conference on VLSI Design, 2015

Parallel two step random walk algorithm to analyze VLSI power grid networks.

Satyabrata Dash, Vivek Bangera, Vinay B. Y. Kumar, Gaurav Trivedi, Sachin B. Patkar

Proceedings of the 19th International Symposium on VLSI Design and Test, 2015

2014

Projective Geometry and precedence constraint based application mapping on multicore network-on-chip systems.

Janak Porwal, Sanket Diwale, Vinay B. Y. Kumar, Sachin B. Patkar

Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014

FPGA-based implementation of M4RM for matrix multiplication over GF(2).

Vivek Kumar, Vinay B. Y. Kumar, Sachin B. Patkar

Proceedings of the 18th International Symposium on VLSI Design and Test, 2014

Storage-allocation to sequential structures in High-Level Synthesis-assisted prototyping.

Vinay B. Y. Kumar, Shovan Maity, Sachin B. Patkar

Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

2013

Solution of PDEs-electrically coupled systems with electrical analogy.

Yogesh Dilip Save, H. Narayanan, Sachin B. Patkar

Integr., 2013

Memory Efficient Implementation of Two Graph Based Circuit Simulator for PDE-Electrical Analogy.

Yogesh Dilip Save, H. Narayanan, Sachin B. Patkar

Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

Hardware-software Scalable Architectures for Gaussian Elimination over GF(2) and Higher Galois Fields.

Prateek Saxena, Vinay B. Y. Kumar, Dilawar Singh, H. Narayanan, Sachin B. Patkar

Proceedings of the PECCS 2013, 2013

2012

Two Graph Based Circuit Simulator for PDE-Electrical Analogy.

Yogesh Dilip Save, H. Narayanan, Sachin B. Patkar

Proceedings of the 25th International Conference on VLSI Design, 2012

FPGA Implementation of Particle Filter Based Object Tracking in Video.

Sumeet Agrawal, Pinal Engineer, Rajbabu Velmurugan, Sachin B. Patkar

Proceedings of the International Symposium on Electronic System Design, 2012

2011

Solution of Partial Differential Equations by electrical analogy.

Yogesh Dilip Save, H. Narayanan, Sachin B. Patkar

J. Comput. Sci., 2011

Double Precision Sparse Matrix Vector Multiplication Accelerator on FPGA.

Sumedh Attarde, Siddharth Joshi, Yash Deshpande, Sunil Puranik, Sachin B. Patkar

Proceedings of the PECCS 2011, 2011

2010

FPGA Based High Performance Double-Precision Matrix Multiplication.

Vinay B. Y. Kumar, Siddharth Joshi, Sachin B. Patkar, H. Narayanan

Int. J. Parallel Program., 2010

Large Scale VLSI Circuit Simulation Using Point Relaxation.

Subhendu Roy, Yogesh Dilip Save, H. Narayanan, Sachin B. Patkar

Proceedings of the 2010 International Conference on Scientific Computing, 2010

2009

Exploiting Hybrid Analysis in Solving Electrical Networks.

V. Siva Sankar, H. Narayanan, Sachin B. Patkar

Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

A Pipelined Simulation Approach for Logic Emulation using Multi-FPGA Platforms.

Dinesh Baviskar, Sachin B. Patkar

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Acceleration of conjugate gradient method for circuit simulation using CUDA.

Anirudh Maringanti, Viraj Athavale, Sachin B. Patkar

Proceedings of the 16th International Conference on High Performance Computing, 2009

2005

Algorithms For Scheduling Of Data Transfer Across FPGAs In A Grid.

Janak Porwal, Sachin B. Patkar

Proceedings of The 2005 International Conference on Engineering of Reconfigurable Systems and Algorithms, 2005

2003

Fast On-Line/Off-Line Algorithms for Optimal Reinforcement of a Network and its Connections with Principal Partition.

Sachin B. Patkar, H. Narayanan

J. Comb. Optim., 2003

Improving graph partitions using submodular functions.

Sachin B. Patkar, H. Narayanan

Discret. Appl. Math., 2003

The realization of finite state machines by decomposition and the principal lattice of partitions of a submodular function.

Madhav P. Desai, H. Narayanan, Sachin B. Patkar

Discret. Appl. Math., 2003

An Efficient Practical Heuristic For Good Ratio-Cut Partitioning.

Sachin B. Patkar, H. Narayanan

Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

2001

A note on optimal covering augmentation for graphic polymatroids.

Sachin B. Patkar, H. Narayanan

Inf. Process. Lett., 2001

Realization of set functions as cut functions of graphs and hypergraphs.

Satoru Fujishige, Sachin B. Patkar

Discret. Math., 2001

1999

Priority Scheduling in Parallel I/O Systems.

C. R. Venugopal, S. S. S. P. Rao, Sachin B. Patkar

Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 1999

1997

A New Partitioning Strategy Based on Supermodular Functions.

Sachin B. Patkar, Shabbir H. Batterywala, M. Chandramouli, H. Narayanan

Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

1996

Approximation Algorithms for Min-k-Overlap Problems Using the Principal Lattice of Partitions Approach.

H. Narayanan, Subir K. Roy, Sachin B. Patkar

J. Algorithms, 1996

1994

Abstract and Generic Rigidity in the Plane.

Sachin B. Patkar, Brigitte Servatius, K. V. Subrahmanyam

J. Comb. Theory, Ser. B, 1994

1992

Principal Lattice of Partition of submodular functions on Graphs: Fast algorithms for Principal Partition and Generic Rigidity.

Sachin B. Patkar, H. Narayanan

Proceedings of the Algorithms and Computation, Third International Symposium, 1992

Fast Sequential and Randomised Parallel Algorithms for Rigidity and approximate Min k-cut.

Sachin B. Patkar, H. Narayanan

Proceedings of the Foundations of Software Technology and Theoretical Computer Science, 1992

1991

A Fast Algorithm for the Principle Partition of a Graph.

Sachin B. Patkar, H. Narayanan

Proceedings of the Foundations of Software Technology and Theoretical Computer Science, 1991