Vinay B. Y. Kumar

Orcid: 0000-0001-8363-2852

According to our database1, Vinay B. Y. Kumar authored at least 18 papers between 2010 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2022
AERO: Design Space Exploration Framework for Resource-Constrained CNN Mapping on Tile-Based Accelerators.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2022

2021
Feeding Three Birds With One Scone: A Generic Duplication Based Countermeasure To Fault Attacks.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020
Towards Designing a Secure RISC-V System-on-Chip: ITUS.
J. Hardw. Syst. Secur., 2020

A Novel Duplication Based Countermeasure To Statistical Ineffective Fault Analysis.
IACR Cryptol. ePrint Arch., 2020

Feeding Three Birds With One Scone: A Generic Duplication Based Countermeasure To Fault Attacks (Extended Version).
IACR Cryptol. ePrint Arch., 2020

Secure Your SoC: Building System-an-Chip Designs for Security.
Proceedings of the 33rd IEEE International System-on-Chip Conference, 2020

Post-Quantum Secure Boot.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
ITUS: A Secure RISC-V System-on-Chip.
Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019

Recruiting Fault Tolerance Techniques for Microprocessor Security.
Proceedings of the 28th IEEE Asian Test Symposium, 2019

2018
Lightweight Forth Programmable NoCs.
Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018

2016
Relaxation Based Circuit Simulation Acceleration over CPU-FPGA.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

2015
Framework for Application Mapping over Packet-Switched Network of FPGAs: Case Studies.
CoRR, 2015

Parallel two step random walk algorithm to analyze VLSI power grid networks.
Proceedings of the 19th International Symposium on VLSI Design and Test, 2015

2014
Projective Geometry and precedence constraint based application mapping on multicore network-on-chip systems.
Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014

FPGA-based implementation of M4RM for matrix multiplication over GF(2).
Proceedings of the 18th International Symposium on VLSI Design and Test, 2014

Storage-allocation to sequential structures in High-Level Synthesis-assisted prototyping.
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

2013
Hardware-software Scalable Architectures for Gaussian Elimination over GF(2) and Higher Galois Fields.
Proceedings of the PECCS 2013, 2013

2010
FPGA Based High Performance Double-Precision Matrix Multiplication.
Int. J. Parallel Program., 2010


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