Yatish Turakhia

Orcid: 0000-0001-5600-2900

According to our database1, Yatish Turakhia authored at least 20 papers between 2013 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
TALCO: Tiling Genome Sequence Alignment Using Convergence of Traceback Pointers.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2024

2023
DecentTree: scalable Neighbour-Joining for the genomic era.
Bioinform., September, 2023

Tracking and curating putative SARS-CoV-2 recombinants with RIVET.
Bioinform., September, 2023

2022
phastSim: Efficient simulation of sequence evolution for pandemic-scale datasets.
PLoS Comput. Biol., 2022

BTE: a Python module for pandemic-scale mutation-annotated phylogenetic trees.
J. Open Source Softw., 2022

matOptimize: a parallel tree optimization method enables online phylogenetics for SARS-CoV-2.
Bioinform., 2022

HiCOMB 2022 Invited Speaker: Pandemic-scale Phylogenetics.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2022

2021
ShUShER: private browser-based placement of sensitive genome samples on phylogenetic trees.
J. Open Source Softw., 2021

2020
Domain-specific hardware accelerators.
Commun. ACM, 2020

SegAlign: a scalable GPU-based whole genome aligner.
Proceedings of the International Conference for High Performance Computing, 2020

2019
Darwin: A Genomics Coprocessor.
IEEE Micro, 2019

Darwin: A Genomics Co-processor Provides up to 15, 000X Acceleration on Long Read Assembly.
Proceedings of the 2019 USENIX Annual Technical Conference, 2019

Parallel Approach to Sliding Window Sums.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2019

Darwin-WGA: A Co-processor Provides Increased Sensitivity in Whole Genome Alignments with High Speedup.
Proceedings of the 25th IEEE International Symposium on High Performance Computer Architecture, 2019

2017
Thread Progress Equalization: Dynamically Adaptive Power-Constrained Performance Optimization of Multi-Threaded Applications.
IEEE Trans. Computers, 2017

HoLiSwap: Reducing Wire Energy in L1 Caches.
CoRR, 2017

2016
Thread Progress Equalization: Dynamically Adaptive Power and Performance Optimization of Multi-threaded Applications.
CoRR, 2016

2015
Framework for Application Mapping over Packet-Switched Network of FPGAs: Case Studies.
CoRR, 2015

2013
Cherry-picking: exploiting process variations in dark-silicon homogeneous chip multi-processors.
Proceedings of the Design, Automation and Test in Europe, 2013

HaDeS: architectural synthesis for <u>h</u>eterogeneous <u>d</u>ark <u>s</u>ilicon chip multi-processors.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013


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