Piotr Zajac

Orcid: 0000-0002-3968-8848

According to our database1, Piotr Zajac authored at least 33 papers between 2002 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2024
Analysis of the accessibility of selected massive open online courses (MOOCs) for users with disabilities.
Univers. Access Inf. Soc., March, 2024

2022
Observation of Readout Temperature Dependence and Its Variability for the MEMS and ASIC System Specimens and Their PCB Testbenches.
Proceedings of the 29th International Conference on Mixed Design of Integrated Circuits and System, 2022

2021
A Capacitive 3-Axis MEMS Accelerometer for Medipost: A Portable System Dedicated to Monitoring Imbalance Disorders.
Sensors, 2021

2020
CMOS Interface for Capacitive Sensors with Custom Fully-Differential Amplifiers.
Proceedings of the 27th International Conference on Mixed Design of Integrated Circuits and System, 2020

2019
Application of Offset Trimming Circuit for Reducing the Impact of Parasitics in Capacitive Sensor Readout Circuit.
Proceedings of the 26th International Conference on Mixed Design of Integrated Circuits and Systems, 2019

De-Identification of Electronic Health Records Data.
Proceedings of the Information Technology in Biomedicine, 2019

2018
Methodology of determining the applicability range of the DPL model to heat transfer in modern integrated circuits comprised of FinFETs.
Microelectron. Reliab., 2018

Novel thermal model of microchannel cooling system designed for fast simulation of liquid-cooled ICs.
Microelectron. Reliab., 2018

Thermal-aware Floorplanning Guidelines for 3D ICs with Integrated Microchannels.
Proceedings of the 25th International Conference "Mixed Design of Integrated Circuits and System", 2018

2017
Peak temperature reduction by optimizing power density distribution in 3D ICs with microchannel cooling.
Microelectron. Reliab., 2017

Thermal coupling phenomenon in ICs cooled by integrated microchannels.
Proceedings of the 24th International Conference Mixed Design of Integrated Circuits and Systems, 2017

Comparative analysis of compact thermal models generated from measured thermal responses and detailed thermal models.
Proceedings of the 24th International Conference Mixed Design of Integrated Circuits and Systems, 2017

2016
Impact of floorplanning and thermal vias placement on temperature in 2D and 3D processors.
Microelectron. J., 2016

Coupled thermo-fluidic simulation for design space exploration of microchannels in liquid-cooled 3D ICs.
Proceedings of the 2016 MIXDES, 2016

2015
Investigation of localized thermal vias for temperature reduction in 3D multicore processors.
Proceedings of the 22nd International Conference Mixed Design of Integrated Circuits & Systems, 2015

Custom method for automation of microbolometer design and simulation.
Proceedings of the 22nd International Conference Mixed Design of Integrated Circuits & Systems, 2015

2014
Evaluating the impact of scaling on temperature in FinFET-technology multicore processors.
Microelectron. J., 2014

Dedicated thermal emulator for analysis of thermal coupling in many-core processors.
Microelectron. J., 2014

The influence of residual stress induced by anodic wafer bonding on MEMS membrane properties.
Proceedings of the 21st International Conference Mixed Design of Integrated Circuits and Systems, 2014

Monte Carlo modeling of stiffness of MEMS membrane.
Proceedings of the 21st International Conference Mixed Design of Integrated Circuits and Systems, 2014

Modelling modern processors using FEM and compact model - A comparative study.
Proceedings of the 21st International Conference Mixed Design of Integrated Circuits and Systems, 2014

2013
New methodology for thermal analysis of multi-core processors based on dedicated ASIC.
Microelectron. J., 2013

Application of a genetic algorithm for dimension optimization of the MEMS-based accelerometer.
Proceedings of the 20th International Conference Mixed Design of Integrated Circuits and Systems, 2013

Influence of Scaling on IC Temperature in FinFET Microprocessor Technologies.
Proceedings of the 20th International Conference Mixed Design of Integrated Circuits and Systems, 2013

2011
Chip Self-Organization and Fault Tolerance in Massively Defective Multicore Arrays.
IEEE Trans. Dependable Secur. Comput., 2011

2009
Enhanced self-configurability and yield in multicore grids.
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009

2008
Fault tolerance through self-configuration in the future nanoscale multiprocessors.
PhD thesis, 2008

Self-Configuration and Reachability Metrics in Massively Defective Multiport Chips.
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008

2007
Resilience, Production Yield and Self-Configuration in the Future Massively Defective Nanochips.
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007

Production Yield and Self-Configuration in the Future Massively Defective Nanochips.
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007

2006
Contribution of Communications to Dependability in Massively-Defective General-Purpose Nanoarchitectures.
Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006

2004
Evaluation of object metrics in a case.
Proceedings of the IASTED International Conference on Software Engineering, 2004

2002
Software Technology for WAP Based M-Commerce - A Comparative Study of Toolkits for the Development of Mobile Applications.
Proceedings of the IADIS International Conference WWW/Internet 2002, 2002


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