Dimitris Gizopoulos
Orcid: 0000-0002-1613-9061
According to our database1,
Dimitris Gizopoulos
authored at least 171 papers
between 1995 and 2024.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 2013, "For contributions to self-testing and on-line error detection of microprocessor architectures".
Timeline
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Online presence:
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Bibliography
2024
Gem5-MARVEL: Microarchitecture-Level Resilience Analysis of Heterogeneous SoC Architectures.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2024
2023
IEEE Trans. Computers, November, 2023
IEEE Trans. Emerg. Top. Comput., 2023
CoRR, 2023
Vitamin-V: Virtual Environment and Tool-boxing for Trustworthy Development of RISC-V based Cloud Services.
CoRR, 2023
NEUROPULS: NEUROmorphic energy-efficient secure accelerators based on Phase change materials aUgmented siLicon photonicS.
CoRR, 2023
Computer, 2023
Proceedings of the 41st IEEE VLSI Test Symposium, 2023
Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023
Estimating the Failures and Silent Errors Rates of CPUs Across ISAs and Microarchitectures.
Proceedings of the IEEE International Test Conference, 2023
Proceedings of the 29th International Symposium on On-Line Testing and Robust System Design, 2023
Energy Efficiency of Out-of-Order CPUs: Comparative Study and Microarchitectural Hotspot Characterization of RISC-V Designs.
Proceedings of the IEEE International Symposium on Workload Characterization, 2023
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2023
EUROPULS: NEUROmorphic energy-efficient secure accelerators based on Phase change materials aUgmented siLicon photonicS.
Proceedings of the IEEE European Test Symposium, 2023
Validation, Verification, and Testing (VVT) of future RISC-V powered cloud infrastructures: the Vitamin-V Horizon Europe Project perspective.
Proceedings of the IEEE European Test Symposium, 2023
VITAMIN-V: Virtual Environment and Tool-Boxing for Trustworthy Development of RISC-V Based Cloud Services.
Proceedings of the 26th Euromicro Conference on Digital System Design, 2023
2022
On the Evaluation of the Total-Cost-of-Ownership Trade-Offs in Edge vs Cloud Deployments: A Wireless-Denial-of-Service Case Study.
IEEE Trans. Sustain. Comput., 2022
IEEE Trans. Sustain. Comput., 2022
Soft Error Effects on Arm Microprocessors: Early Estimations versus Chip Measurements.
IEEE Trans. Computers, 2022
IDLD: Instantaneous Detection of Leakage and Duplication of Identifiers used for Register Renaming.
Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022
gpuFI-4: A Microarchitecture-Level Framework for Assessing the Cross-Layer Resilience of Nvidia GPUs.
Proceedings of the International IEEE Symposium on Performance Analysis of Systems and Software, 2022
2021
A System-Level Voltage/Frequency Scaling Characterization Framework for Multicore CPUs.
CoRR, 2021
The Impact of SoC Integration and OS Deployment on the Reliability of Arm Processors.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2021
Demystifying the System Vulnerability Stack: Transient Fault Effects Across the Layers.
Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021
Boosting Microprocessor Efficiency: Circuit- and Workload-Aware Assessment of Timing Errors.
Proceedings of the IEEE International Symposium on Workload Characterization, 2021
Characterizing Soft Error Vulnerability of CPUs Across Compiler Optimizations and Microarchitectures.
Proceedings of the IEEE International Symposium on Workload Characterization, 2021
2020
CoRR, 2020
Proceedings of the 50th Annual IEEE-IFIP International Conference on Dependable Systems and Networks, 2020
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
2019
SyRA: Early System Reliability Analysis for Cross-Layer Soft Errors Resilience in Memory Arrays of Microprocessor Systems.
IEEE Trans. Computers, 2019
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2019
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019
Proceedings of the IEEE International Symposium on Workload Characterization, 2019
Adaptive Voltage/Frequency Scaling and Core Allocation for Balanced Energy and Performance on Multicore CPUs.
Proceedings of the 25th IEEE International Symposium on High Performance Computer Architecture, 2019
Demystifying Soft Error Assessment Strategies on ARM CPUs: Microarchitectural Fault Injection vs. Neutron Beam Experiments.
Proceedings of the 49th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2019
2018
IEEE Comput. Archit. Lett., 2018
Multi-faceted microarchitecture level reliability characterization for NVIDIA and AMD GPUs.
Proceedings of the 36th IEEE VLSI Test Symposium, 2018
Micro-Viruses for Fast System-Level Voltage Margins Characterization in Multicore CPUs.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2018
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018
Proceedings of the 36th IEEE International Conference on Computer Design, 2018
Proceedings of the 48th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops, 2018
An energy-efficient and error-resilient server ecosystem exceeding conservative scaling limits.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
2017
Proceedings of the 35th IEEE VLSI Test Symposium, 2017
Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017
Microarchitecture level reliability comparison of modern GPU designs: First findings.
Proceedings of the 2017 IEEE International Symposium on Performance Analysis of Systems and Software, 2017
MeRLiN: Exploiting Dynamic Instruction Behavior for Fast and Accurate Microarchitecture Level Reliability Assessment.
Proceedings of the 44th Annual International Symposium on Computer Architecture, 2017
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017
RT Level vs. Microarchitecture-Level Reliability Assessment: Case Study on ARM(R) Cortex(R)-A9 CPU.
Proceedings of the 47th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops, 2017
2016
Int. J. Parallel Program., 2016
Microprocessor reliability-performance tradeoffs assessment at the microarchitecture level.
Proceedings of the 34th IEEE VLSI Test Symposium, 2016
Proceedings of the 34th IEEE VLSI Test Symposium, 2016
Proceedings of the 2016 IEEE International Test Conference, 2016
Proceedings of the 2016 IEEE International Symposium on Performance Analysis of Systems and Software, 2016
Proceedings of the 2016 IEEE International Symposium on Performance Analysis of Systems and Software, 2016
Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016
ISA-independent post-silicon validation for the address translation mechanisms of modern microprocessors.
Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016
Unveiling difficult bugs in address translation caching arrays for effective post-silicon validation.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016
2015
Cross-layer reliability evaluation, moving from the hardware architecture to the system level: A CLERECO EU project overview.
Microprocess. Microsystems, 2015
IEEE Des. Test, 2015
Efficient parallelization of the Discrete Wavelet Transform algorithm using memory-oblivious optimizations.
Proceedings of the 25th International Workshop on Power and Timing Modeling, 2015
Bayesian network early reliability evaluation analysis for both permanent and transient faults.
Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015
Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015
Proceedings of the 2015 IEEE International Symposium on Workload Characterization, 2015
Proceedings of the 20th IEEE European Test Symposium, 2015
Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2015
2014
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014
Quantum Inf. Comput., 2014
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014
Special session 8B - Panel: In-field testing of SoC devices: Which solutions by which players?
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014
Power-aware optimization of software-based self-test for L1 caches in microprocessors.
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014
Versatile architecture-level fault injection framework for reliability evaluation: A first report.
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014
2013
Software-Based Self Test Methodology for On-Line Testing of L1 Caches in Multithreaded Multicore Architectures.
IEEE Trans. Very Large Scale Integr. Syst., 2013
Guest Editorial - Special Issue on Manufacturable and Dependable Multicore Architectures at Nanoscale (MEDIAN).
J. Electron. Test., 2013
Proceedings of the 31st IEEE VLSI Test Symposium, 2013
Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013
Measuring the performance impact of permanent faults in modern microprocessor architectures.
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013
Assessing the impact of hard faults in performance components of modern microprocessors.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013
Proceedings of the Design, Automation and Test in Europe, 2013
2012
IEEE Trans. Very Large Scale Integr. Syst., 2012
IEEE Trans. Very Large Scale Integr. Syst., 2012
IEEE Trans. Dependable Secur. Comput., 2012
Proceedings of the 17th IEEE European Test Symposium, 2012
2011
IEEE Trans. Dependable Secur. Comput., 2011
IEEE Trans. Computers, 2011
Proceedings of the 44rd Annual IEEE/ACM International Symposium on Microarchitecture, 2011
Proceedings of the 2011 IEEE International Test Conference, 2011
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011
Proceedings of the Design, Automation and Test in Europe, 2011
2010
IEEE Trans. Very Large Scale Integr. Syst., 2010
Proceedings of the 2011 IEEE International Test Conference, 2010
A software-based self-test methodology for in-system testing of processor cache tag arrays.
Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010
SBST for on-line detection of hard faults in multiprocessor applications under energy constraints.
Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010
Proceedings of the 28th International Conference on Computer Design, 2010
2009
Instruction-Based Online Periodic Self-Testing of Microprocessors with Floating-Point Units.
IEEE Trans. Dependable Secur. Comput., 2009
Online Periodic Self-Test Scheduling for Real-Time Processor-Based Systems Dependability Enhancement.
IEEE Trans. Dependable Secur. Comput., 2009
IEEE Trans. Computers, 2009
Test Program Generation for Communication Peripherals in Processor-Based SoC Devices.
IEEE Des. Test Comput., 2009
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009
Proceedings of the 14th IEEE European Test Symposium, 2009
2008
IEEE Trans. Very Large Scale Integr. Syst., 2008
An Input Vector Monitoring Concurrent BIST Architecture Based on a Precomputed Test Set.
IEEE Trans. Computers, 2008
IEEE Des. Test Comput., 2008
Proceedings of the 2008 IEEE International Test Conference, 2008
Proceedings of the Design, Automation and Test in Europe, 2008
Proceedings of the Design, Automation and Test in Europe, 2008
Proceedings of the Design, Automation and Test in Europe, 2008
2007
Guest Editorial: Special Section on "Autonomous Silicon Validation and Testing of Microprocessors and Microprocessor-Based Systems".
IEEE Trans. Very Large Scale Integr. Syst., 2007
IEEE Trans. Very Large Scale Integr. Syst., 2007
A methodology for detecting performance faults in microprocessors via performance monitoring hardware.
Proceedings of the 2007 IEEE International Test Conference, 2007
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007
Proceedings of the 12th European Test Symposium, 2007
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007
2006
Testability Analysis and Scalable Test Generation for High-Speed Floating-Point Units.
IEEE Trans. Computers, 2006
Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006
Optimal periodic testing of intermittent faults in embedded pipelined processor applications.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
Proceedings of the 43rd Design Automation Conference, 2006
2005
Accumulator-based test generation for robust sequential fault testing in DSP cores in near-optimal time.
IEEE Trans. Very Large Scale Integr. Syst., 2005
IEEE Trans. Reliab., 2005
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005
Effective software-based self-test strategies for on-line periodic testing of embedded processors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005
A concurrent BIST scheme for on-line/off-line testing based on a pre-computed test set.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005
2004
Low-cost, on-line self-testing of processor cores based on embedded software routines.
Microelectron. J., 2004
IEEE Des. Test Comput., 2004
2003
IEEE Commun. Mag., 2003
Application and Analysis of RT-Level Software-Based Self-Testing for Embedded Processor Cores.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003
Proceedings of the 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 2003
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003
Proceedings of the 2003 Design, 2003
2002
Proceedings of the 2002 Design, 2002
2001
J. Electron. Test., 2001
Robust and Low-Cost BIST Architectures for Sequential Fault Testing in Datapath Multipliers.
Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001
Proceedings of the Conference on Design, Automation and Test in Europe, 2001
2000
Sequential Fault Modeling and Test Pattern Generation for CMOS Iterative Logic Arrays.
IEEE Trans. Computers, 2000
IEEE Des. Test Comput., 2000
Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000
Deterministic Built-In Self -Test for Shifters, Adders and ALUs in Datapaths.
Proceedings of the 1st Latin American Test Workshop, 2000
1999
IEEE Trans. Computers, 1999
Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999
Proceedings of the 1999 Design, 1999
1998
Test Generation and Fault Simulation for Cell Fault Model using Stuck-at Fault Model based Test Tools.
J. Electron. Test., 1998
Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998
1997
Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997
Proceedings of the Proceedings IEEE International Test Conference 1997, 1997
1996
Αρχιτεκτονική επαναληπτικών διατάξεων λογικής σε τεχνολογία COS VLSI με τεχνικές σχεδίασης αυξημένης δοκιμαστικόητας
PhD thesis, 1996
Integr., 1996
Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996
Proceedings of the Proceedings IEEE International Test Conference 1996, 1996
1995
Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995
Proceedings of the Proceedings IEEE International Test Conference 1995, 1995
Proceedings of the 4th Asian Test Symposium (ATS '95), 1995