Po-Hsun Wu

Orcid: 0000-0002-4892-5905

According to our database1, Po-Hsun Wu authored at least 18 papers between 2011 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2022
Robust H<sub>∞</sub> Observer-Based Reference Tracking Control Design of Nonlinear Stochastic Systems: HJIE-Embedded Deep Learning Approach.
IEEE Access, 2022

2021
Robust H<sub>∞</sub> Deep Neural Network-Based Filter Design of Nonlinear Stochastic Signal Systems.
IEEE Access, 2021

2019
Auto-focus pathology microscope using sub-array sampling.
Proceedings of the IEEE International Instrumentation and Measurement Technology Conference, 2019

2016
Parasitic-Aware Common-Centroid FinFET Placement and Routing for Current-Ratio Matching.
ACM Trans. Design Autom. Electr. Syst., 2016

2015
A Novel Analog Physical Synthesis Methodology Integrating Existent Design Expertise.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Common-Centroid FinFET Placement Considering the Impact of Gate Misalignment.
Proceedings of the 2015 Symposium on International Symposium on Physical Design, ISPD 2015, Monterey, CA, USA, March 29, 2015

Analog layout synthesis with knowledge mining.
Proceedings of the European Conference on Circuit Theory and Design, 2015

2014
Exploring Feasibilities of Symmetry Islands and Monotonic Current Paths in Slicing Trees for Analog Placement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Placement optimization of flexible TFT circuits with mechanical strain and temperature consideration.
ACM J. Emerg. Technol. Comput. Syst., 2014

Triangle-based process hotspot classification with dummification in EUVL.
Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014

A topology-based ECO routing methodology for mask cost minimization.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
1-D Cell Generation With Printability Enhancement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Bus-driven floorplanning with thermal consideration.
Integr., 2013

Lithography-aware 1-dimensional cell generation.
Proceedings of the 21st European Conference on Circuit Theory and Design, 2013

A novel cell placement algorithm for flexible TFT circuit with mechanical strain and temperature consideration.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012
Bus-driven floorplanning with bus pin assignment and deviation minimization.
Integr., 2012

Performance-driven analog placement considering monotonic current paths.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

2011
Thermal-aware bus-driven floorplanning.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011


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