Tung-Chieh Chen

According to our database1, Tung-Chieh Chen authored at least 38 papers between 2005 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2019
MDP-trees: multi-domain macro placement for ultra large-scale mixed-size designs.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018
NTUplace4dr: A Detailed-Routing-Driven Placer for Mixed-Size Circuit Designs With Technology and Region Constraints.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

FastPass: Fast timing path search for generalized timing exception handling.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017
Blockage-aware terminal propagation for placement wirelength minimization.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

An integrated-spreading-based macro-refining algorithm for large-scale mixed-size circuit designs.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

A novel damped-wave framework for macro placement.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

2015
A Novel Analog Physical Synthesis Methodology Integrating Existent Design Expertise.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

A Fast Prototyping Framework for Analog Layout Migration With Planar Preservation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

An approach to anchoring and placing high performance custom digital designs.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
Exploring Feasibilities of Symmetry Islands and Monotonic Current Paths in Slicing Trees for Analog Placement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

NTUplace4h: A Novel Routability-Driven Placement Algorithm for Hierarchical Mixed-Size Circuit Designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

2013
1-D Cell Generation With Printability Enhancement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Efficient analog layout prototyping by layout reuse with routing preservation.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Lithography-aware 1-dimensional cell generation.
Proceedings of the 21st European Conference on Circuit Theory and Design, 2013

Routability-driven placement for hierarchical mixed-size circuit designs.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Double patterning lithography-aware analog placement.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012
Challenges and solutions in modern analog placement.
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012

Performance-driven analog placement considering monotonic current paths.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

2011
Automated placement for custom digital designs.
Proceedings of the 2011 International Symposium on Physical Design, 2011

Fast analog layout prototyping for nanometer design migration.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

2009
Essential Issues in Analytical Placement Algorithms.
IPSJ Trans. System LSI Design Methodology, 2009

2008
Packing Floorplan Representations.
Proceedings of the Handbook of Algorithms for Physical Design Automation., 2008

MP-Trees: A Packing-Based Macro Placement Algorithm for Modern Mixed-Size Designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

NTUplace3: An Analytical Placer for Large-Scale Mixed-Size Designs With Preplaced Blocks and Density Constraints.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Metal-Density-Driven Placement for CMP Variation and Routability.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

A New Multilevel Framework for Large-Scale Interconnect-Driven Floorplanning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Effective Wire Models for X-Architecture Placement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

An integrated nonlinear placement framework with congestion and porosity aware buffer planning.
Proceedings of the 45th Design Automation Conference, 2008

2007
X-architecture placement based on effective wire models.
Proceedings of the 2007 International Symposium on Physical Design, 2007

MP-trees: A Packing-Based Macro Placement Algorithm for Mixed-Size Designs.
Proceedings of the 44th Design Automation Conference, 2007

NTUplace3: An Analytical Placer for Large-Scale Mixed-Size Designs.
Proceedings of the Modern Circuit Placement, Best Practices and Results, 2007

2006
Modern Floorplanning Based on B<sup>*</sup>-Tree and Fast Simulated Annealing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

NTUplace2: a hybrid placer using partitioning and analytical techniques.
Proceedings of the 2006 International Symposium on Physical Design, 2006

A high-quality mixed-size analytical placer considering preplaced blocks and density constraints.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

2005
NTUplace: a ratio partitioning based placement algorithm for large-scale mixed-size designs.
Proceedings of the 2005 International Symposium on Physical Design, 2005

Modern floorplanning based on fast simulated annealing.
Proceedings of the 2005 International Symposium on Physical Design, 2005

IMF: interconnect-driven multilevel floorplanning for large-scale building-module designs.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

SoC test scheduling using the B-tree based floorplanning technique.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005


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