Mark Po-Hung Lin

According to our database, Mark Po-Hung Lin authored at least 61 papers between 2007 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Reinforcement Learning or Simulated Annealing for Analog Placement? A Study based on Bounded-Sliceline Grids.

Mark Po-Hung Lin, Chou-Chen Lee, Yi-Chao Hsieh

Proceedings of the 2024 International Symposium on Physical Design, 2024

2023

On Reducing LDE Variations in Modern Analog Placement.

A. K. Thasreefa, Abhishek Patyal, Hao-Yu Chi, Mark Po-Hung Lin, Hung-Ming Chen

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2023

Pole-Aware Analog Layout Synthesis Considering Monotonic Current Flows and Wire Crossings.

Abhishek Patyal, Hung-Ming Chen, Mark Po-Hung Lin, Guan-Qi Fang, Simon Yi-Hung Chen

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023

Layout Synthesis of Analog Primitive Cells with Variational Autoencoder.

Po-Chun Wang, Mark Po-Hung Lin, Chien-Nan Jimmy Liu, Hung-Ming Chen

Proceedings of the 19th International Conference on Synthesis, 2023

Late Breaking Results: PVT-Sensitive Delay Fitting for High-Performance Computing.

Ding-Hao Wang, Shuo-Hung Hsu, Shu-Hsiang Yang, Pei-Ju Lin, Hui-Ting Yang, Mark Po-Hung Lin

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

On Automating Finger-Cap Array Synthesis with Optimal Parasitic Matching for Custom SAR ADC.

Cheng-Yu Chiang, Chia-Lin Hu, Mark Po-Hung Lin, Yu-Szu Chung, Shyh-Jye Jou, Jieh-Tsorng Wu, Shiuh-Hua Wood Chiang, Chien-Nan Jimmy Liu, Hung-Ming Chen

Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

2022

Dataset of SSIOE (Self-Supervised Indoor Occupancy Estimation for Intelligent Building Management).

Sin-Han Huang, Tzu-Yin Chao, Mark Po-Hung Lin, Ching-Chun Huang

Dataset, May, 2022

On Optimizing Capacitor Array Design for Advanced Node SAR ADC.

Cheng-Yu Chiang, Chia-Lin Hu, Kang-Yu Chang, Mark Po-Hung Lin, Shyh-Jye Jou, Hung-Yu Chen, Chien-Nan Jimmy Liu, Hung-Ming Chen

Proceedings of the 18th International Conference on Synthesis, 2022

Automatic Analog Schematic Diagram Generation based on Building Block Classification and Reinforcement Learning.

Hung-Yun Hsu, Mark Po-Hung Lin

Proceedings of the 2022 ACM/IEEE Workshop on Machine Learning for CAD, 2022

Common-Centroid Layout for Active and Passive Devices: A Review and the Road Ahead.

Nibedita Karmokar, Meghna Madhusudan, Arvind K. Sharma, Ramesh Harjani, Mark Po-Hung Lin, Sachin S. Sapatnekar

Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

2021

Massive Figure Extraction and Classification in Electronic Component Datasheets for Accelerating PCB Design Preparation.

Kuan-Chun Chen, Chou-Chen Lee, Mark Po-Hung Lin, Yan-Jhih Wang, Yi-Ting Chen

Proceedings of the 3rd ACM/IEEE Workshop on Machine Learning for CAD, 2021

A Novel Machine-Learning based SoC Performance Monitoring Methodology under Wide-Range PVT Variations with Unknown Critical Paths.

Ding-Hao Wang, Pei-Ju Lin, Hui-Ting Yang, Ching-An Hsu, Sin-Han Huang, Mark Po-Hung Lin

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

A Novel Technology Mapper for Complex Universal Gates.

Meng-Che Wu, Ai Quoc Dao, Mark Po-Hung Lin

Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020

Corner-Stitching-Based Multilayer Obstacle-Avoiding Component-to-Component Rectilinear Minimum Spanning Tree Construction.

Yen-Yu Su, Shuo-Hui Wang, Wei-Liang Wu, Mark Po-Hung Lin

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Overview of 2020 CAD Contest at ICCAD.

Ing-Chao Lin, Ulf Schlichtmann, Tsung-Wei Huang, Mark Po-Hung Lin

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

Achieving Analog Layout Integrity through Learning and Migration Invited Talk.

Mark Po-Hung Lin, Hao-Yu Chi, Abhishek Patyal, Zheng-Yao Liu, Jun-Jie Zhao, Chien-Nan Jimmy Liu, Hung-Ming Chen

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

Late Breaking Results: Automatic Adaptive MOM Capacitor Cell Generation for Analog and Mixed-Signal Layout Design.

Tzu-Wei Wang, Po-Chang Wu, Mark Po-Hung Lin

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

Late Breaking Results: Pole-aware Analog Placement Considering Monotonic Current Flow and Crossing-Wire Minimization.

Abhishek Patyal, Hung-Ming Chen, Mark Po-Hung Lin

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019

Overview of 2019 CAD Contest at ICCAD.

Ulf Schlichtmann, Sabya Das, Ing-Chao Lin, Mark Po-Hung Lin

Proceedings of the International Conference on Computer-Aided Design, 2019

IR-aware Power Net Routing for Multi-Voltage Mixed-Signal Design.

Shuo-Hui Wang, Guan-Hong Liou, Yen-Yu Su, Mark Po-Hung Lin

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018

SAT-Based Fault Equivalence Checking in Functional Safety Verification.

Ai Quoc Dao, Mark Po-Hung Lin, Alan Mishchenko

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Classifying Analog and Digital Circuits with Machine Learning Techniques Toward Mixed-Signal Design Automation.

Guan-Hong Liou, Shuo-Hui Wang, Yan-Yu Su, Mark Po-Hung Lin

Proceedings of the 15th International Conference on Synthesis, 2018

Efficient computation of ECO patch functions.

Ai Quoc Dao, Nian-Ze Lee, Li-Cheng Chen, Mark Po-Hung Lin, Jie-Hong R. Jiang, Alan Mishchenko, Robert K. Brayton

Proceedings of the 55th Annual Design Automation Conference, 2018

2017

Matched-Routing Common-Centroid 3-D MOM Capacitors for Low-Power Data Converters.

Pang-Yen Chou, Nai-Chen Chen, Mark Po-Hung Lin, Helmut Graeb

IEEE Trans. Very Large Scale Integr. Syst., 2017

An Efficient Two-Phase ILP-Based Algorithm for Precise CMOS RFIC Layout Generation.

Tsun-Ming Tseng, Bing Li, Ching-Feng Yeh, Hsiang-Chieh Jhan, Zuo-Min Tsai, Mark Po-Hung Lin, Ulf Schlichtmann

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Parasitic-Aware Common-Centroid Binary-Weighted Capacitor Layout Generation Integrating Placement, Routing, and Unit Capacitor Sizing.

Mark Po-Hung Lin, Vincent Wei-Hao Hsiao, Chun-Yu Lin, Nai-Chen Chen

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Minimizing detection-to-boosting latency toward low-power error-resilient circuits.

Chih-Cheng Hsu, Masanori Hashimoto, Mark Po-Hung Lin

Integr., 2017

AIsim: Functional Simulator for Analog-to-Information Perceptual Systems.

Hong Liu, Zheyu Liu, Fei Qiao, Mark Po-Hung Lin, Qi Wei, Huazhong Yang

Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

State retention for power gated design with non-uniform multi-bit retention latches.

Guo-Gin Fan, Mark Po-Hung Lin

Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

High-density MOM capacitor array with novel mortise-tenon structure for low-power SAR ADC.

Nai-Chen Chen, Pang-Yen Chou, Helmut E. Graeb, Mark Po-Hung Lin

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016

Parasitic-Aware Common-Centroid FinFET Placement and Routing for Current-Ratio Matching.

Po-Hsun Wu, Mark Po-Hung Lin, Xin Li, Tsung-Yi Ho

ACM Trans. Design Autom. Electr. Syst., 2016

DeMixGen: Deterministic Mixed-Signal Layout Generation With Separated Analog and Digital Signal Paths.

Mark Po-Hung Lin, Po-Hsun Chang, Shuenn-Yuh Lee, Helmut E. Graeb

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Latch Clustering for Minimizing Detection-to-Boosting Latency Toward Low-Power Resilient Circuits.

Chih-Cheng Hsu, Mark Po-Hung Lin, Masanori Hashimoto

Proceedings of the 18th System Level Interconnect Prediction Workshop, 2016

Novel CMOS RFIC layout generation with concurrent device placement and fixed-length microstrip routing.

Tsun-Ming Tseng, Bing Li, Ching-Feng Yeh, Hsiang-Chieh Jhan, Zuo-Min Tsai, Mark Po-Hung Lin, Ulf Schlichtmann

Proceedings of the 53rd Annual Design Automation Conference, 2016

Recent research development and new challenges in analog layout synthesis.

Mark Po-Hung Lin, Yao-Wen Chang, Chih-Ming Hung

Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015

A Novel Analog Physical Synthesis Methodology Integrating Existent Design Expertise.

Po-Hsun Wu, Mark Po-Hung Lin, Tung-Chieh Chen, Ching-Feng Yeh, Xin Li, Tsung-Yi Ho

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Clock-Tree Aware Multibit Flip-Flop Generation During Placement for Power Optimization.

Mark Po-Hung Lin, Chih-Cheng Hsu, Yu-Chuan Chen

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Crosstalk-aware multi-bit flip-flop generation for power optimization.

Chih-Cheng Hsu, Mark Po-Hung Lin, Yao-Tsung Chang

Integr., 2015

Low-power gated clock tree optimization for three-dimensional integrated circuits.

Yu-Chuan Chen, Chih-Cheng Hsu, Mark Po-Hung Lin

Proceedings of the VLSI Design, Automation and Test, 2015

Common-Centroid FinFET Placement Considering the Impact of Gate Misalignment.

Po-Hsun Wu, Mark Po-Hung Lin, Xin Li, Tsung-Yi Ho

Proceedings of the 2015 Symposium on International Symposium on Physical Design, ISPD 2015, Monterey, CA, USA, March 29, 2015

Analog layout synthesis with knowledge mining.

Po-Hsun Wu, Mark Po-Hung Lin, Tsung-Yi Ho

Proceedings of the European Conference on Circuit Theory and Design, 2015

2014

Exploring Feasibilities of Symmetry Islands and Monotonic Current Paths in Slicing Trees for Analog Placement.

Po-Hsun Wu, Mark Po-Hung Lin, Tung-Chieh Chen, Ching-Feng Yeh, Tsung-Yi Ho, Bin-Da Liu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Power optimization for clock network with clock gate cloning and flip-flop merging.

Shih-Chuan Lo, Chih-Cheng Hsu, Mark Po-Hung Lin

Proceedings of the International Symposium on Physical Design, 2014

More effective power-gated circuit optimization with multi-bit retention registers.

Shu-Hung Lin, Mark Po-Hung Lin

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

Parasitic-aware Sizing and Detailed Routing for Binary-weighted Capacitors in Charge-scaling DAC.

Mark Po-Hung Lin, Vincent Wei-Hao Hsiao, Chun-Yu Lin

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013

1-D Cell Generation With Printability Enhancement.

Po-Hsun Wu, Mark Po-Hung Lin, Tung-Chieh Chen, Tsung-Yi Ho, Yu-Chuan Chen, Shun-Ren Siao, Shu-Hung Lin

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Common-Centroid Capacitor Layout Generation Considering Device Matching and Parasitic Minimization.

Mark Po-Hung Lin, Yi-Ting He, Vincent Wei-Hao Hsiao, Rong-Guey Chang, Shuenn-Yuh Lee

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

In-placement clock-tree aware multi-bit flip-flop generation for power optimization.

Chih-Cheng Hsu, Yu-Chuan Chen, Mark Po-Hung Lin

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Lithography-aware 1-dimensional cell generation.

Po-Hsun Wu, Mark Po-Hung Lin, Tung-Chieh Chen, Tsung-Yi Ho, Yu-Chuan Chen

Proceedings of the 21st European Conference on Circuit Theory and Design, 2013

2012

Performance-driven analog placement considering monotonic current paths.

Po-Hsun Wu, Mark Po-Hung Lin, Yang-Ru Chen, Bing-Shiun Chou, Tung-Chieh Chen, Tsung-Yi Ho, Bin-Da Liu

Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

Crosstalk-aware power optimization with multi-bit flip-flops.

Chih-Cheng Hsu, Yao-Tsung Chang, Mark Po-Hung Lin

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011

Thermal-Driven Analog Placement Considering Device Matching.

Mark Po-Hung Lin, Hongbo Zhang, Martin D. F. Wong, Yao-Wen Chang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Post-Placement Power Optimization With Multi-Bit Flip-Flops.

Mark Po-Hung Lin, Chih-Cheng Hsu, Yao-Tsung Chang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Automated synthesis of discrete-time sigma-delta modulators from system architecture to circuit netlist.

Shuenn-Yuh Lee, Chih-Yuan Chen, Jia-Hua Hong, Rong-Guey Chang, Mark Po-Hung Lin

Microelectron. J., 2011

A corner stitching compliant B^∗-tree representation and its applications to analog placement.

Hui-Fang Tsao, Pang-Yen Chou, Shih-Lun Huang, Yao-Wen Chang, Mark Po-Hung Lin, Duan-Ping Chen, Dick Liu

Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Recent research in analog placement considering thermal gradient.

Mark Po-Hung Lin

Proceedings of the 20th European Conference on Circuit Theory and Design, 2011

2010

Post-placement power optimization with multi-bit flip-flops.

Yao-Tsung Chang, Chih-Cheng Hsu, Mark Po-Hung Lin, Yu-Wen Tsai, Sheng-Fong Chen

Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

2009

Analog Placement Based on Symmetry-Island Formulation.

Mark Po-Hung Lin, Yao-Wen Chang, Shyh-Chang Lin

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Analog layout synthesis - Recent advances in topological approaches.

Helmut Gräb, Florin Balasa, Rafael Castro-López, Yu-Wei Chang, Francisco V. Fernández, Mark Po-Hung Lin, Martin Strasser

Proceedings of the Design, Automation and Test in Europe, 2009

2008

Analog placement based on hierarchical module clustering.

Mark Po-Hung Lin, Shyh-Chang Lin

Proceedings of the 45th Design Automation Conference, 2008

2007

Analog Placement Based on Novel Symmetry-Island Formulation.

Mark Po-Hung Lin, Shyh-Chang Lin

Proceedings of the 44th Design Automation Conference, 2007