Prithwish Basu Roy

Orcid: 0000-0003-2025-6102

According to our database1, Prithwish Basu Roy authored at least 9 papers between 2022 and 2025.

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Bibliography

2025
Veritas: Deterministic Verilog Code Synthesis from LLM-Generated Conjunctive Normal Form.
CoRR, June, 2025

VeriLeaky: Navigating IP Protection vs Utility in Fine-Tuning for LLM-Driven Verilog Coding.
CoRR, March, 2025

GLLaMoR: Graph-based Logic Locking by Large Language Models for Enhanced Robustness.
Proceedings of the 43rd IEEE VLSI Test Symposium, 2025

Educational Framework for Power Side-Channel Attacks on Neural Networks in Embedded Systems.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

2024
NiLoPher: Breaking a Modern SAT-Hardened Logic-Locking Scheme via Power Analysis Attack.
IACR Cryptol. ePrint Arch., 2024

Attacks and Countermeasures for Digital Microfluidic Biochips - Extended Abstract.
Proceedings of the Security, Privacy, and Applied Cryptography Engineering, 2024

Offramps: An FPGA-Based Intermediary for Analysis and Modification of Additive Manufacturing Control Systems.
Proceedings of the 54th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2024

2023
A survey of Digital Manufacturing Hardware and Software Trojans.
CoRR, 2023

2022
Avatar: Reinforcing Fault Attack Countermeasures in EDA with Fault Transformations.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022


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