Xin Zhang
Orcid: 0000-0002-0579-2268Affiliations:
- Columbia University, Department of Electrical Engineering, New York City, NY, USA (since 2021)
- IBM T. J. Watson Research Center, Yorktown Heights, NY, USA (since 2014)
- Agency for Science, Technology and Research (A*STAR), Institute of Microelectronics, Singapore (2013)
- University of California, Berkeley, CA, USA (2012)
- University of Tokyo, Institute of Industrial Science, Tokyo, Japan (2008 - 2012)
- Peking University, Beijing (PhD 2008)
According to our database1,
Xin Zhang authored at least 76 papers
between 2006 and 2026.
Collaborative distances:
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Bibliography
2026
Towards Generalizable and Efficient Circuit Topology Design: A Graph-Transformer-based Surrogate Model with Curriculum Learning.
ACM Trans. Design Autom. Electr. Syst., July, 2026
Design of a Wide-Loading-Range Cap-Less LDO With Enhanced Power Supply Rejection and Speed.
IEEE Trans. Circuits Syst. I Regul. Pap., April, 2026
CoRR, April, 2026
Steady-State and Small-Signal Analysis of High-Ratio Hybrid Buck Converters With Enhancement to State-Space-Averaging Methodology.
IEEE Trans. Circuits Syst. I Regul. Pap., February, 2026
Proactive Power Management-Based Supply Regulation with Online Learning for Variation-Tolerant Workload-Aware Droop Mitigation in 28nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2026
2025
FlexDCIM: A 400 MHz 249.1 TOPS/W 64 Kb Flexible Digital Compute-in-Memory SRAM Macro for CNN Acceleration.
IEEE Trans. Circuits Syst. I Regul. Pap., October, 2025
Digital In-Memory Compute for Machine Learning Applications With Input and Model Security.
IEEE J. Solid State Circuits, September, 2025
A 65-nm Proactive Power Management Technique With Real-Time Machine Learning Engine for Droop Prediction and Mitigation on Microprocessors.
IEEE J. Solid State Circuits, June, 2025
Semiconductor SEM Image Defect Classification Using Supervised and Semi-Supervised Learning with Vision Transformers.
CoRR, June, 2025
SESOMP: A Scalable and Energy-Efficient Self-Organizing Map Processor for IoT Devices.
IEEE J. Solid State Circuits, May, 2025
CoRR, February, 2025
Power-Limited Inference Performance Optimization Using a Software-Assisted Peak Current Regulation Scheme in a 5-nm AI SoC.
IEEE J. Solid State Circuits, January, 2025
Digital Low-Dropout Regulator-Assisted Buck DC-DC Converter Achieving 68-mV Droop Voltage and 95.5% Efficiency.
IEEE Solid State Circuits Lett., 2025
A 14-nm Energy-Efficient and Reconfigurable Analog Current-Domain In-Memory Compute SRAM Accelerator.
Proceedings of the 38th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems, 2025
9.6 A 6.78MHz Single-Stage Regulating Rectifier with Dual Outputs Simultaneously Charged in a Half Cycle Achieving 92.2% Efficiency and 131mW Output Power.
Proceedings of the IEEE International Solid-State Circuits Conference, 2025
Efficient Circuit Performance Prediction Using Machine Learning: From Schematic to Layout and Silicon Measurement with Minimal Data Input.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025
AUTOCIRCUIT-RL: Reinforcement Learning-Driven LLM for Automated Circuit Topology Generation.
Proceedings of the Forty-second International Conference on Machine Learning, 2025
LaMAGIC2: Advanced Circuit Formulations for Language Model-Based Analog Topology Generation.
Proceedings of the Forty-second International Conference on Machine Learning, 2025
A Multi-Level Power Management Architecture for Battery-Powered SPAD Drivers with Supply Intrinsic Quenching and 10-ns Dead Time.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2025
A 93.9% Peak Efficiency 3V-to-40V-Input GaN-based DC-DC Converter with Unified Reliability and Efficiency Adaptive Control.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2025
2024
A 96.1% Efficiency Single-Inductor Multiple-Output (SIMO) Buck Converter With 2.1-A/ns Transient Speed and 2.2-A Maximum Current Capacity.
IEEE J. Solid State Circuits, August, 2024
A Ten-Level Series-Capacitor 24-to-1-V DC-DC Converter With Fast In Situ Efficiency Tracking, Power-FET Code Roaming, and Switch Node Power Rail.
IEEE J. Solid State Circuits, July, 2024
CoRR, 2024
CoRR, 2024
CoRR, 2024
14.1 A Software-Assisted Peak Current Regulation Scheme to Improve Power-Limited Inference Performance in a 5nm AI SoC.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
A 24/48V to 0.8V-1.2V All-Digital Synchronous Buck Converter with Package-Integrated GaN power FETs and 180nm Silicon Controller IC.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
Proceedings of the Forty-first International Conference on Machine Learning, 2024
Graph-Transformer-based Surrogate Model for Accelerated Converter Circuit Topology Design.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024
A Monolithic 3-Level Single-Inductor Multiple-Output Buck Converter with State-Based Non-Linear Control Capable of Handling 1A/1.5ns Transient with On-Die LC.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2024
A Secure Digital In-Memory Compute (IMC) Macro with Protections for Side-Channel and Bus Probing Attacks.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2024
2023
A Digital Bit-Reconfigurable Versatile Compute-In-Memory Macro for Machine Learning Acceleration.
IEEE Trans. Circuits Syst. II Express Briefs, May, 2023
ACM Trans. Design Autom. Electr. Syst., March, 2023
A 90.4% Peak Efficiency 48-to-1-V GaN/Si Hybrid Converter With Three-Level Hybrid Dickson Topology and Gradient Descent Run-Time Optimizer.
IEEE J. Solid State Circuits, 2023
Proactive Power Regulation with Real-time Prediction and Fast Response Guardband for Fine-grained Dynamic Voltage Droop Mitigation on Digital SoCs.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
A Switched-Capacitor Integer Compute Unit with Decoupled Storage and Arithmetic for Cloud AI Inference in 5nm CMOS.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
A Single-Inductor 4-Phase Hybrid Switched-Capacitor Topology for Integrated 48V-to-1V DC-DC Converters.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
93.89% Peak Efficiency 24V-to-1V DC-DC Converter with Fast In-Situ Efficiency Tracking and Power-FET Code Roaming.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023
A 65nm Fully-integrated Fast-switching Buck Converter with Resonant Gate Drive and Automatic Tracking.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
A 400MHz 249.1TOPS/W 64Kb Fully-Reconfigurable SRAM-Based Digital Compute-in-Memory Macro for Accelerating CNNs.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023
SESOMP: A Scalable and Energy-Efficient Self-Organizing Map Processor with Computing-In-Memory and Dead Neuron Pruning.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023
2022
A 7-nm Four-Core Mixed-Precision AI Chip With 26.2-TFLOPS Hybrid-FP8 Training, 104.9-TOPS INT4 Inference, and Workload-Aware Throttling.
IEEE J. Solid State Circuits, 2022
A 90.4% Peak Efficiency 48V/1V Three-Level Hybrid Dickson Converter with Gradient Descent Run-Time Optimizer and GaN/Si Hybrid Conversion.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
Proceedings of the 19th International SoC Design Conference, 2022
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022
2021
Guest Editorial Cross-Layer Designs, Methodologies, and Systems to Enable Micro AI for On-Device Intelligence.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2021
A Survey on the Optimization of Neural Network Accelerators for Micro-AI On-Device Inference.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2021
A 7nm 4-Core AI Chip with 25.6TFLOPS Hybrid FP8 Training, 102.4TOPS INT4 Inference and Workload-Aware Throttling.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021
From Specification to Topology: Automatic Power Converter Design via Reinforcement Learning.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021
2020
Non-isolated 48V-to-1V Heterogeneous Integrated Voltage Converters for High Performance Computing in Data Centers.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020
2019
IEEE J. Emerg. Sel. Topics Circuits Syst., 2019
A 48 V Input 0.75 V Output DC-DC Converter Power Block for HPC Systems and Datacenters (invited paper).
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
2015
An Ultra-Low Voltage Level Shifter Using Revised Wilson Current Mirror for Fast and Energy-Efficient Wide-Range Voltage Conversion from Sub-Threshold to I/O Voltage.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
An Ultralow-Voltage Sensor Node Processor With Diverse Hardware Acceleration and Cognitive Sampling for Intelligent Sensing.
IEEE Trans. Circuits Syst. II Express Briefs, 2015
Proceedings of the European Conference on Circuit Theory and Design, 2015
2014
IEEE J. Solid State Circuits, 2014
30.7 A 60Mb/s wideband BCC transceiver with 150pJ/b RX and 31pJ/b TX for emerging wearable applications.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
2013
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
2012
On-Chip Measurement System for Within-Die Delay Variation of Individual Standard Cells in 65-nm CMOS.
IEEE Trans. Very Large Scale Integr. Syst., 2012
A 1-V-Input Switched-Capacitor Voltage Converter With Voltage-Reference-Free Pulse-Density Modulation.
IEEE Trans. Circuits Syst. II Express Briefs, 2012
An 80 mV Startup Dual-Mode Boost Converter by Charge-Pumped Pulse Generator and Threshold Voltage Tuned Oscillator With Hot Carrier Injection.
IEEE J. Solid State Circuits, 2012
Startup Techniques for 95 mV Step-Up Converter by Capacitor Pass-On Scheme and V<sub>TH</sub>-Tuned Oscillator With Fixed Charge Programming.
IEEE J. Solid State Circuits, 2012
A 0.45-V input on-chip gate boosted (OGB) buck converter in 40-nm CMOS with more than 90% efficiency in load range from 2µW to 50µW.
Proceedings of the Symposium on VLSI Circuits, 2012
A 120-mV input, fully integrated dual-mode charge pump in 65-nm CMOS for thermoelectric energy harvester.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012
2011
Post-Silicon Clock Deskew Employing Hot-Carrier Injection Trimming With On-Chip Skew Monitoring and Auto-Stressing Scheme for Sub/Near Threshold Digital Circuits.
IEEE Trans. Circuits Syst. II Express Briefs, 2011
A Variable Output Voltage Switched-Capacitor DC-DC Converter with Pulse Density and Width Modulation (PDWM) for 57% Ripple Reduction at Low Output Voltage.
IEICE Trans. Electron., 2011
0.5-V Input Digital Low-Dropout Regulator (LDO) with 98.7% Current Efficiency in 65 nm CMOS.
IEICE Trans. Electron., 2011
0.18-V Input Charge Pump with Forward Body Bias to Startup Boost Converter for Energy Harvesting Applications.
IEICE Trans. Electron., 2011
A 95mV-startup step-up converter with Vth-tuned oscillator by fixed-charge programming and capacitor pass-on scheme.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
A 80-mV input, fast startup dual-mode boost converter with charge-pumped pulse generator for energy harvesting.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011
An on-chip characterizing system for within-die delay variation measurement of individual standard cells in 65-nm CMOS.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011
2010
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010
0.5-V input digital LDO with 98.7% current efficiency and 2.7-µA quiescent current in 65nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010
0.18-V input charge pump with forward body biasing in startup circuit using 65nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010
2006
A CMOS Differential Difference Amplifier with Reduced Nonlinearity Error of Interpolation for Interpolating ADCs.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006