Yuhao Ju
Orcid: 0000-0003-2509-400X
According to our database1,
Yuhao Ju authored at least 16 papers
between 2020 and 2026.
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Bibliography
2026
A Physics-Informed Neural Network Surrogate for Runtime PDN and Dynamic Droop Prediction in 2.5-D Chiplet Integration.
IEEE Trans. Very Large Scale Integr. Syst., April, 2026
LLA: Enhancing Security and Privacy for Generative Models with Logic-Locked Accelerators.
Proceedings of the Fortieth AAAI Conference on Artificial Intelligence, 2026
2025
A 65 nm General-Purpose Compute-in-Memory Processor Supporting Both General Programming and Deep Learning Tasks.
IEEE J. Solid State Circuits, April, 2025
Mobile-PBR: A 28-nm Energy-Efficient Rendering Processor for Photorealistic Augmented Reality With Inverse Rendering and Background Clustering.
IEEE J. Solid State Circuits, January, 2025
Development of a Physics-Informed Neural Network Model for Rapid Power Integrity Analysis in Die-Level and Die-Package Co-Design for 2.5-D Chiplet Solutions.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2025
Modeling, Design and In-situ Demonstration of Bio-inspired Central Pattern Generator and Neuromorphic Computing Circuits for Complex Kinematic Control of Quadruped Robots.
Proceedings of the Great Lakes Symposium on VLSI 2025, GLSVLSI 2025, New Orleans, LA, USA, 30 June 2025, 2025
2024
Scalable Physics-Embedded Neural Networks for Real-Time Robotic Control in Embedded Systems.
Proceedings of the 67th IEEE International Midwest Symposium on Circuits and Systems, 2024
20.4 A 28nm Physics Computing Unit Supporting Emerging Physics-Informed Neural Network and Finite Element Method for Real-Time Scientific Computing on Edge Devices.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
LLM-MARK: A Computing Framework on Efficient Watermarking of Large Language Models for Authentic Use of Generative AI at Local Devices.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024
2023
A Systolic Neural CPU Processor Combining Deep Learning and General-Purpose Computing With Enhanced Data Locality and End-to-End Performance.
IEEE J. Solid State Circuits, 2023
A General-Purpose Compute-in-Memory Processor Combining CPU and Deep Learning with Elevated CPU Efficiency and Enhanced Data Locality.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
2022
A 65nm Systolic Neural CPU Processor for Combined Deep Learning and General-Purpose Computing with 95% PE Utilization, High Data Locality and Enhanced End-to-End Performance.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
A Differentiable Neural Computer for Logic Reasoning with Scalable Near-Memory Computing and Sparsity Based Enhancement.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022
2021
A Dynamic Timing Enhanced DNN Accelerator With Compute-Adaptive Elastic Clock Chain Technique.
IEEE J. Solid State Circuits, 2021
2020
NCPU: An Embedded Neural CPU Architecture on Resource-Constrained Low Power Devices for Real-time End-to-End Performance.
Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020
31.3 A Compute-Adaptive Elastic Clock-Chain Technique with Dynamic Timing Enhancement for 2D PE-Array-Based Accelerators.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020