Qubo Hu

According to our database1, Qubo Hu authored at least 9 papers between 2004 and 2008.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
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Links

On csauthors.net:

Bibliography

2008
Guidance of Loop Ordering for Reduced Memory Usage in Signal Processing Applications.
J. Signal Process. Syst., 2008

Storage Estimation and Design Space Exploration Methodologies for the Memory Management of Signal Processing Applications.
J. Signal Process. Syst., 2008

2007
Hierarchical Memory Size Estimation for Loop Transformation and Data Memory Platform Optimization.
PhD thesis, 2007

Incremental hierarchical memory size estimation for steering of loop transformations.
ACM Trans. Design Autom. Electr. Syst., 2007

Bit-Width Constrained Memory Hierarchy Optimization for Real-Time Video Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Fast memory footprint estimation based on maximal dependency vector calculation.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006
Polyhedral space generation and memory estimation from interface and memory models of real-time video systems.
J. Syst. Softw., 2006

Hierarchical memory size estimation for loop fusion and loop shifting in data-dominated applications.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2004
Memory Requirement Optimization with Loop Fusion and Loop Shifting.
Proceedings of the 2004 Euromicro Symposium on Digital Systems Design (DSD 2004), Architectures, Methods and Tools, 31 August, 2004


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