Martin Palkovic

According to our database1, Martin Palkovic authored at least 35 papers between 2002 and 2017.

Collaborative distances:



In proceedings 
PhD thesis 




The ANTAREX tool flow for monitoring and autotuning energy efficient HPC systems.
Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017

Autotuning and adaptivity approach for energy efficient Exascale HPC systems: The ANTAREX approach.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

The ANTAREX approach to autotuning and adaptivity for energy efficient HPC systems.
Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016

ANTAREX - AutoTuning and Adaptivity appRoach for Energy Efficient eXascale HPC Systems.
Proceedings of the 18th IEEE International Conference on Computational Science and Engineering, 2015

Design Flow for Silicon Chip Implementing Novel Platform Architecture for Wireless Communication.

DART - a High Level Software-Defined Radio Platform Model for Developing the Run-Time Controller.
Signal Processing Systems, 2012

Power Estimation at Different Abstraction Levels for Wireless Baseband Processors.
J. Low Power Electronics, 2012

A flexible platform architecture for Gbps wireless communication.
Proceedings of the 2012 International Symposium on System on Chip, 2012

Partitioning and Assignment Exploration for Multiple Modes of IEEE 802.11n Modem on Heterogeneous MPSoC Platforms.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

A multi-threaded coarse-grained array processor for wireless baseband.
Proceedings of the IEEE 9th Symposium on Application Specific Processors, 2011

Invited paper: Parallel programming and run-time resource management framework for many-core platforms: The 2PARMA approach.
Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2011

Dart - a high level software-defined radio platform model for developing the run-time controller.
Proceedings of the IEEE International Conference on Acoustics, 2011

Future Software-Defined Radio Platforms and Mapping Flows.
IEEE Signal Process. Mag., 2010

Trade-offs in loop transformations.
ACM Trans. Design Autom. Electr. Syst., 2009

System-scenario-based design of dynamic embedded systems.
ACM Trans. Design Autom. Electr. Syst., 2009

Dealing with data dependent conditions to enable general global source code transformations.
IJES, 2009

Parallelization exploration of wireless applications using MPA.
Proceedings of the Parallel Computing: From Multicores and GPU's to Petascale, 2009

Experience with widening based equivalence checking in realistic multimedia systems.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2009

System-level power/performance evaluation of 3D stacked DRAMs for mobile applications.
Proceedings of the Design, Automation and Test in Europe, 2009

Guidance of Loop Ordering for Reduced Memory Usage in Signal Processing Applications.
Signal Processing Systems, 2008

Storage Estimation and Design Space Exploration Methodologies for the Memory Management of Signal Processing Applications.
Signal Processing Systems, 2008

Mapping of 40 MHz MIMO SDM-OFDM Baseband Processing on Multi-Processor SDR Platform.
Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008

Incremental hierarchical memory size estimation for steering of loop transformations.
ACM Trans. Design Autom. Electr. Syst., 2007

Bit-Width Constrained Memory Hierarchy Optimization for Real-Time Video Systems.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

Fast memory footprint estimation based on maximal dependency vector calculation.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Polyhedral space generation and memory estimation from interface and memory models of real-time video systems.
Journal of Systems and Software, 2006

Hierarchical memory size estimation for loop fusion and loop shifting in data-dominated applications.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

Loop Transformation Methodologies for Array-Oriented Memory Management.
Proceedings of the 2006 IEEE International Conference on Application-Specific Systems, 2006

Global Memory Optimisation for Embedded Systems Allowed by Code Duplication.
Proceedings of the 9th International Workshop on Software and Compilers for Embedded Systems, Dallas, Texas, USA, September 29, 2005

Systematic Preprocessing of Data Dependent Constructs for Embedded Systems.
Proceedings of the Integrated Circuit and System Design, 2005

Memory Requirement Optimization with Loop Fusion and Loop Shifting.
Proceedings of the 2004 Euromicro Symposium on Digital Systems Design (DSD 2004), Architectures, Methods and Tools, 31 August, 2004

Systematic Address and Control Code Transformations for Performance Optimisation of a MPEG-4 Video Decoder.
Proceedings of the ASPDAC 2002 / VLSI Design 2002, 2002

Systematic Power-Performance Trade-Off in MPEG-4 by Means of Selective Function Inlining Steered by Address Optimization Opportunities.
Proceedings of the 2002 Design, 2002