Rajeev Barua

Affiliations:
  • University of Maryland, College Park, USA


According to our database1, Rajeev Barua authored at least 60 papers between 1996 and 2021.

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Bibliography

2021
RL-BIN++: Overcoming Binary Instrumentation Challenges in the Presence of Obfuscation Techniques and Problematic Features.
Proceedings of the ICSCA 2021, 2021

2018
Easy PRAM-Based High-Performance Parallel Programming with ICE.
IEEE Trans. Parallel Distributed Syst., 2018

A Hybrid Static Tool to Increase the Usability and Scalability of Dynamic Detection of Malware.
Proceedings of the 13th International Conference on Malicious and Unwanted Software, 2018

2017
DynODet: Detecting Dynamic Obfuscation in Malware.
Proceedings of the Detection of Intrusions and Malware, and Vulnerability Assessment, 2017

RL-Bin, Robust Low-overhead Binary Rewriter.
Proceedings of the 2017 Workshop on Forming an Ecosystem Around Software Transformation, 2017

2016
A Stack Memory Abstraction and Symbolic Analysis Framework for Executables.
ACM Trans. Softw. Eng. Methodol., 2016

Transparently Space Sharing a Multicore Among Multiple Processes.
ACM Trans. Parallel Comput., 2016

POSTER: Easy PRAM-based High-Performance Parallel Programming with ICE.
Proceedings of the 2016 International Conference on Parallel Architectures and Compilation, 2016

2015
Affine Parallelization Using Dependence and Cache Analysis in a Binary Rewriter.
IEEE Trans. Parallel Distributed Syst., 2015

Instruction-Cache Locking for Improving Embedded Systems Performance.
ACM Trans. Embed. Comput. Syst., 2015

2014
Lazy Scheduling: A Runtime Adaptive Scheduler for Declarative Parallelism.
ACM Trans. Program. Lang. Syst., 2014

Affine Loop Optimization Based on Modulo Unrolling in Chapel.
Proceedings of the 8th International Conference on Partitioned Global Address Space Programming Models, 2014

Affine Parallelization of Loops with Run-Time Dependent Bounds from Binaries.
Proceedings of the Programming Languages and Systems, 2014

Recovery of Object Oriented Features from C++ Binaries.
Proceedings of the 21st Asia-Pacific Software Engineering Conference, 2014

2013
MemSafe: ensuring the spatial and temporal memory safety of C at runtime.
Softw. Pract. Exp., 2013

Implementation and performance evaluation of a distributed conjugate gradient method in a cloud computing environment.
Softw. Pract. Exp., 2013

Static binary rewriting without supplemental information: Overcoming the tradeoff between coverage and correctness.
Proceedings of the 20th Working Conference on Reverse Engineering, 2013

Scalable variable and data type detection in a binary rewriter.
Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation, 2013

Efficient multiprogramming for multicores with SCAF.
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture, 2013

An Accurate Stack Memory Abstraction and Symbolic Analysis Framework for Executables.
Proceedings of the 2013 IEEE International Conference on Software Maintenance, 2013

A compiler-level intermediate representation based binary analysis and rewriting system.
Proceedings of the Eighth Eurosys Conference 2013, 2013

2011
Resource-Aware Compiler Prefetching for Fine-Grained Many-Cores.
Int. J. Parallel Program., 2011

Retrofitting Security in COTS Software with Binary Rewriting.
Proceedings of the Future Challenges in Security and Privacy for Academia and Industry, 2011

Toolchain for Programming, Simulating and Studying the XMT Many-Core Architecture.
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011

Improving Run-Time Scheduling for General-Purpose Parallel Code.
Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011

2010
Lazy binary-splitting: a run-time adaptive work-stealing scheduler.
Proceedings of the 15th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2010

Automatic Parallelization in a Binary Rewriter.
Proceedings of the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 2010

Resource-Aware Compiler Prefetching for Many-Cores.
Proceedings of the Ninth International Symposium on Parallel and Distributed Computing, 2010

2009
Memory allocation for embedded systems with a compile-time-unknown scratch-pad size.
ACM Trans. Embed. Comput. Syst., 2009

Instruction cache locking inside a binary rewriter.
Proceedings of the 2009 International Conference on Compilers, 2009

2008
MTSS: Multitask stack sharing for embedded systems.
ACM Trans. Embed. Comput. Syst., 2008

2007
Scratch-pad memory allocation without compiler support for java applications.
Proceedings of the 2007 International Conference on Compilers, 2007

Recursive function data allocation to scratch-pad memory.
Proceedings of the 2007 International Conference on Compilers, 2007

2006
Dynamic allocation for scratch-pad memory using compile-time decisions.
ACM Trans. Embed. Comput. Syst., 2006

Memory overflow protection for embedded systems using run-time checks, reuse, and compression.
ACM Trans. Embed. Comput. Syst., 2006

An integrated scratch-pad allocator for affine and non-affine code.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005
Dynamic Functional Unit Assignment for Low Power.
J. Supercomput., 2005

Reducing code size in VLIW instruction scheduling.
J. Embed. Comput., 2005

Heap data allocation to scratch-pad memory in embedded systems.
J. Embed. Comput., 2005

Segment protection for embedded systems using run-time checks.
Proceedings of the 2005 International Conference on Compilers, 2005

MTSS: multi task stack sharing for embedded systems.
Proceedings of the 2005 International Conference on Compilers, 2005

2004
Execution History Guided Instruction Prefetching.
J. Supercomput., 2004

Memory overflow protection for embedded systems using run-time checks, reuse and compression.
Proceedings of the 2004 International Conference on Compilers, 2004

2003
Contention-Free Periodic Message Scheduler Medium Access Control in Wireless Sensor / Actuator Networks.
Proceedings of the 24th IEEE Real-Time Systems Symposium (RTSS 2003), 2003

Compiler-decided dynamic memory allocation for scratch-pad based embedded systems.
Proceedings of the International Conference on Compilers, 2003

Dynamic Functional Unit Assignment for Low Power.
Proceedings of the Embedded Software for SoC, 2003

2002
An optimal memory allocation scheme for scratch-pad-based embedded systems.
ACM Trans. Embed. Comput. Syst., 2002

Compiler-directed customization of ASIP cores.
Proceedings of the Tenth International Symposium on Hardware/Software Codesign, 2002

2001
Compiler Support for Scalable and Efficient Memory Systems.
IEEE Trans. Computers, 2001

Optimal Tiling for Minimizing Communication in Distributed Shared-Memory Multiprocessors.
Proceedings of the Compiler Optimizations for Scalable Parallel Systems Languages, 2001

Heterogeneous memory management for embedded systems.
Proceedings of the 2001 International Conference on Compilers, 2001

2000
Compiler-managed memory system for software-exposed architectures.
PhD thesis, 2000

1999
Maps: A Compiler-Managed Memory System for Raw Machines.
Proceedings of the 26th Annual International Symposium on Computer Architecture, 1999

Parallelizing Applications into Silicon.
Proceedings of the 7th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '99), 1999

1998
The Sensitivity of Communication Mechanisms to Bandwidth and Latency.
Proceedings of the Fourth International Symposium on High-Performance Computer Architecture, Las Vegas, Nevada, USA, January 31, 1998

Memory bank disambiguation using modulo unrolling for Raw machines.
Proceedings of the 5th International Conference On High Performance Computing, 1998

Space-Time Scheduling of Instruction-Level Parallelism on a Raw Machine.
Proceedings of the ASPLOS-VIII Proceedings of the 8th International Conference on Architectural Support for Programming Languages and Operating Systems, 1998

1997
Baring It All to Software: Raw Machines.
Computer, 1997

The RAW benchmark suite: computation structures for general purpose computing.
Proceedings of the 5th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '97), 1997

1996
Communication-Minimal Partitioning of Parallel Loops and Data Arrays for Cache-Coherent Distributed-Memory Multiprocessors.
Proceedings of the Languages and Compilers for Parallel Computing, 1996


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