Michael B. Taylor

Orcid: 0000-0002-4074-6347

Affiliations:
  • University of Washington, Paul Allen School of Computer Science and Engineering, Seattle, WA, USA (since 2017)
  • University of California, San Diego, CA, USA (2005-2016)
  • Massachusetts Institute of Technology (MIT), Cambridge, MA, USA (PhD 2007)


According to our database1, Michael B. Taylor authored at least 74 papers between 1997 and 2023.

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Bibliography

2023
RISE: RISC-V SoC for En/Decryption Acceleration on the Edge for Homomorphic Encryption.
IEEE Trans. Very Large Scale Integr. Syst., October, 2023

Chiplet Cloud: Building AI Supercomputers for Serving Large Generative Language Models.
CoRR, 2023

NeuriCam: Key-Frame Video Super-Resolution and Colorization for IoT Cameras.
Proceedings of the 29th Annual International Conference on Mobile Computing and Networking, 2023

ProcessorFuzz: Processor Fuzzing with Control and Status Registers Guidance.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2023

Beyond Static Parallel Loops: Supporting Dynamic Task Parallelism on Manycore Architectures with Software-Managed Scratchpad Memories.
Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2023

2022
A Tensor Processing Framework for CPU-Manycore Heterogeneous Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

The BlackParrot BedRock Cache Coherence System.
CoRR, 2022

ProcessorFuzz: Guiding Processor Fuzzing using Control and Status Registers.
CoRR, 2022

NeuriCam: Video Super-Resolution and Colorization Using Key Frames.
CoRR, 2022

RACE: RISC-V SoC for En/decryption Acceleration on the Edge for Homomorphic Computation.
Proceedings of the ISLPED '22: ACM/IEEE International Symposium on Low Power Electronics and Design, Boston, MA, USA, August 1, 2022

2021
Pure tensor program rewriting via access patterns (representation pearl).
Proceedings of the MAPS@PLDI 2021: Proceedings of the 5th ACM SIGPLAN International Symposium on Machine Programming, 2021

η-LSTM: Co-Designing Highly-Efficient Large LSTM Training via Exploiting Memory-Saving and Architectural Design Opportunities.
Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021

Taming the Zoo: The Unified GraphIt Compiler Framework for Novel Architectures.
Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021

DirectFuzz: Automated Test Generation for RTL Designs using Directed Graybox Fuzzing.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

Q-VR: system-level design for future mobile collaborative virtual reality.
Proceedings of the ASPLOS '21: 26th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2021

2020
BlackParrot: An Agile Open-Source RISC-V Multicore for Accelerator SoCs.
IEEE Micro, 2020

A 7.3 M Output Non-Zeros/J, 11.7 M Output Non-Zeros/GB Reconfigurable Sparse Matrix-Matrix Multiplication Accelerator.
IEEE J. Solid State Circuits, 2020

ASIC clouds: specializing the datacenter for planet-scale applications.
Commun. ACM, 2020

NoC Symbiosis : (Special Session Paper).
Proceedings of the 14th IEEE/ACM International Symposium on Networks-on-Chip, 2020

Ruche Networks: Wire-Maximal, No-Fuss NoCs : Special Session Paper.
Proceedings of the 14th IEEE/ACM International Symposium on Networks-on-Chip, 2020

Your Agile Open Source HW Stinks (Because It Is Not a System).
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

2019
Technical perspective: Bootstrapping a future of open source, specialized hardware.
Commun. ACM, 2019

A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor With Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

A 7.3 M Output Non-Zeros/J Sparse Matrix-Matrix Multiplication Accelerator using Memory Reconfiguration in 40 nm.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

2018
Extreme Datacenter Specialization for Planet-Scale Computing: ASIC Clouds.
ACM SIGOPS Oper. Syst. Rev., 2018

The Celerity Open-Source 511-Core RISC-V Tiered Accelerator Fabric: Fast Architectures and Design Methodologies for Fast Chips.
IEEE Micro, 2018

The BaseJump Manycore Accelerator Network.
CoRR, 2018

Hiding Intermittent Information Leakage with Architectural Support for Blinking.
Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018

Basejump STL: systemverilog needs a standard template library for hardware design.
Proceedings of the 55th Annual Design Automation Conference, 2018

2017
Specializing a Planet's Computation: ASIC Clouds.
IEEE Micro, 2017

The Evolution of Bitcoin Hardware.
Computer, 2017

Moonwalk: NRE Optimization in ASIC Clouds.
Proceedings of the Twenty-Second International Conference on Architectural Support for Programming Languages and Operating Systems, 2017

2016
Power Side Channels in Security ICs: Hardware Countermeasures.
CoRR, 2016

ASIC Clouds: Specializing the Datacenter.
Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016

BlackBox: lightweight security monitoring for COTS binaries.
Proceedings of the 2016 International Symposium on Code Generation and Optimization, 2016

2014
Exploring Energy Scalability in Coprocessor-Dominated Architectures for Dark Silicon.
ACM Trans. Embed. Comput. Syst., 2014

Quality Time: A simple online technique for quantifying multicore execution efficiency.
Proceedings of the 2014 IEEE International Symposium on Performance Analysis of Systems and Software, 2014

CortexSuite: A synthetic brain benchmark suite.
Proceedings of the 2014 IEEE International Symposium on Workload Characterization, 2014

2013
Dark Silicon [Guest editors' introduction].
IEEE Micro, 2013

A Landscape of the New Dark Silicon Design Regime.
IEEE Micro, 2013

TimeCube: A manycore embedded processor with interference-agnostic progress tracking.
Proceedings of the 2013 International Conference on Embedded Computer Systems: Architectures, 2013

DR-SNUCA: An energy-scalable dynamically partitioned cache.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

Skadu: Efficient vector shadow memories for poly-scopic program analysis.
Proceedings of the 2013 IEEE/ACM International Symposium on Code Generation and Optimization, 2013

Bitcoin and the age of Bespoke Silicon.
Proceedings of the International Conference on Compilers, 2013

2012
The Kremlin Oracle for Sequential Code Parallelization.
IEEE Micro, 2012

Is dark silicon useful?: harnessing the four horsemen of the coming dark silicon apocalypse.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

GreenDroid: An architecture for the Dark Silicon Age.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011
The GreenDroid Mobile Application Processor: An Architecture for Silicon's Dark Future.
IEEE Micro, 2011

Greendroid: Exploring the next evolution in smartphone application processors.
IEEE Commun. Mag., 2011

Kremlin: like gprof, but for parallelization.
Proceedings of the 16th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2011

Kremlin: rethinking and rebooting gprof for the multicore age.
Proceedings of the 32nd ACM SIGPLAN Conference on Programming Language Design and Implementation, 2011

Kismet: parallel speedup estimates for serial programs.
Proceedings of the 26th Annual ACM SIGPLAN Conference on Object-Oriented Programming, 2011

QsCores: trading dark silicon for scalable energy efficiency with quasi-specific cores.
Proceedings of the 44rd Annual IEEE/ACM International Symposium on Microarchitecture, 2011

Efficient complex operators for irregular codes.
Proceedings of the 17th International Conference on High-Performance Computer Architecture (HPCA-17 2011), 2011

Parkour: Parallel Speedup Estimates for Serial Programs.
Proceedings of the 3rd USENIX Workshop on Hot Topics in Parallelism, 2011

An Evaluation of Selective Depipelining for FPGA-Based Energy-Reducing Irregular Code Coprocessors.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

Reducing the Energy Cost of Irregular Code Bases in Soft Processor Systems.
Proceedings of the IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines, 2011

Unifying manycore and FPGA processing with the RUSH architecture.
Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems, 2011

2010
GreenDroid: A mobile application processor for a future of dark silicon.
Proceedings of the 2010 IEEE Hot Chips 22 Symposium, Stanford, CA, USA, August 22-24, 2010, 2010

Conservation cores: reducing the energy of mature computations.
Proceedings of the 15th International Conference on Architectural Support for Programming Languages and Operating Systems, 2010

2009

Energy and switch area optimizations for FPGA global routing architectures.
ACM Trans. Design Autom. Electr. Syst., 2009

SD-VBS: The San Diego Vision Benchmark Suite.
Proceedings of the 2009 IEEE International Symposium on Workload Characterization, 2009

2008
Advancing supercomputer performance through interconnection topology synthesis.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

2007
Tiled microprocessors.
PhD thesis, 2007

Runtime Checking for Program Verification.
Proceedings of the Runtime Verification, 7th International Workshop, 2007

FPGA global routing architecture optimization using a multicommodity flow approach.
Proceedings of the 25th International Conference on Computer Design, 2007

2005
Scalar Operand Networks.
IEEE Trans. Parallel Distributed Syst., 2005

2004
Evaluation of the Raw Microprocessor: An Exposed-Wire-Delay Architecture for ILP and Streams.
Proceedings of the 31st International Symposium on Computer Architecture (ISCA 2004), 2004

2003
Energy characterization of a tiled architecture processor with on-chip networks.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

Scalar Operand Networks: On-Chip Interconnect for ILP in Partitioned Architecture.
Proceedings of the Ninth International Symposium on High-Performance Computer Architecture (HPCA'03), 2003

2002
The Raw Microprocessor: A Computational Fabric for Software Circuits and General-Purpose Programs.
IEEE Micro, 2002

1997
Baring It All to Software: Raw Machines.
Computer, 1997

The RAW benchmark suite: computation structures for general purpose computing.
Proceedings of the 5th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '97), 1997


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