Rajesh Gupta

Affiliations:
  • IBM East Fishkill, Hopewell Junction, NY, USA
  • University of Southern California, Los Angeles, CA, USA
  • IIT, Madras, India


According to our database1, Rajesh Gupta authored at least 10 papers between 1989 and 1995.

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Bibliography

1995
Partial scan design of register-transfer level circuits.
J. Electron. Test., 1995

PEPPER - a timing driven early floorplanner.
Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995

1993
Optimal Configuring of Multiple Scan Chains.
IEEE Trans. Computers, 1993

1992
Testability properties of acyclic structures and applications to partial scan design.
Proceedings of the 10th IEEE VLSI Test Symposium (VTS'92), 1992

Configuring multiple scan chains for minimum test time.
Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

SIESTA: a multi-facet scan design system.
Proceedings of the conference on European design automation, 1992

1991
Ordering Storage Elements in a Single Scan Chain.
Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

1990
The BALLAST Methodology for Structured Partial Scan Design.
IEEE Trans. Computers, 1990

1989
An Object-Oriented VLSI CAD Framework: A Case Study in Rapid Prototyping.
Computer, 1989

BALLAST: a methodology for partial scan design.
Proceedings of the Nineteenth International Symposium on Fault-Tolerant Computing, 1989


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