Melvin A. Breuer

According to our database, Melvin A. Breuer authored at least 188 papers between 1962 and 2016.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of two.

2016

Testable MUTEX Design.

Yang Zhang, Leandro S. Heck, Matheus T. Moreira, David Zar, Melvin A. Breuer, Ney Laert Vilar Calazans, Peter A. Beerel

IEEE Trans. Circuits Syst. I Regul. Pap., 2016

2015

GlYFF: A framework for global yield and floorplan aware design optimization.

Shuo Wang, Yue Gao, Melvin A. Breuer

Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

Design and Analysis of Testable Mutual Exclusion Elements.

Yang Zhang, Leandro S. Heck, Matheus T. Moreira, David Zar, Melvin A. Breuer, Ney Laert Vilar Calazans, Peter A. Beerel

Proceedings of the 21st IEEE International Symposium on Asynchronous Circuits and Systems, 2015

Blade - A Timing Violation Resilient Asynchronous Template.

Dylan Hand, Matheus Trevisan Moreira, Hsin-Ho Huang, Danlei Chen, Frederico Butzke, Zhichao Li, Matheus Gibiluka, Melvin A. Breuer, Ney Laert Vilar Calazans, Peter A. Beerel

Proceedings of the 21st IEEE International Symposium on Asynchronous Circuits and Systems, 2015

Performance Optimization and Analysis of Blade Designs under Delay Variability.

Dylan Hand, Hsin-Ho Huang, Benmao Cheng, Yang Zhang, Matheus Trevisan Moreira, Melvin A. Breuer, Ney Laert Vilar Calazans, Peter A. Beerel

Proceedings of the 21st IEEE International Symposium on Asynchronous Circuits and Systems, 2015

2013

Trading off area, yield and performance via hybrid redundancy in multi-core architectures.

Yue Gao, Yang Zhang, Da Cheng, Melvin A. Breuer

Proceedings of the 31st IEEE VLSI Test Symposium, 2013

Using explicit output comparisons for fault tolerant scheduling (FTS) on modern high-performance processors.

Yue Gao, Sandeep K. Gupta, Melvin A. Breuer

Proceedings of the Design, Automation and Test in Europe, 2013

A new paradigm for trading off yield, area and performance to enhance performance per wafer.

Yue Gao, Melvin A. Breuer, Yanzhi Wang

Proceedings of the Design, Automation and Test in Europe, 2013

2012

Error Rate Estimation for Defective Circuits via Ones Counting.

Zhaoliang Pan, Melvin A. Breuer

ACM Trans. Design Autom. Electr. Syst., 2012

Efficient Overdetection Elimination of Acceptable Faults for Yield Improvement.

Kuen-Jong Lee, Tong-Yu Hsieh, Melvin A. Breuer

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

A design flow to maximize yield/area of physical devices via redundancy.

Mohammad Mirza-Aghatabar, Melvin A. Breuer, Sandeep K. Gupta

Proceedings of the 2012 IEEE International Test Conference, 2012

Theory of redundancy for logic circuits to maximize yield/area.

Mohammad Mirza-Aghatabar, Melvin A. Breuer, Sandeep K. Gupta, Shahin Nazarian

Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

2011

An Error-Tolerance-Based Test Methodology to Support Product Grading for Yield Enhancement.

Tong-Yu Hsieh, Kuen-Jong Lee, Melvin A. Breuer

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

2010

Algorithms to maximize yield and enhance yield/area of pipeline circuitry by insertion of switches and redundant modules.

Mohammad Mirza-Aghatabar, Melvin A. Breuer, Sandeep K. Gupta

Proceedings of the Design, Automation and Test in Europe, 2010

Hardware that produces bounded rather than exact results.

Melvin A. Breuer

Proceedings of the 47th Design Automation Conference, 2010

HYPER: A Heuristic for Yield/Area imProvEment Using Redundancy in SoC.

Mohammad Mirza-Aghatabar, Melvin A. Breuer, Sandeep K. Gupta

Proceedings of the 19th IEEE Asian Test Symposium, 2010

2009

Tolerance of performance degrading faults for effective yield improvement.

Tong-Yu Hsieh, Melvin A. Breuer, Murali Annavaram, Sandeep K. Gupta, Kuen-Jong Lee

Proceedings of the 2009 IEEE International Test Conference, 2009

SIRUP: Switch Insertion in RedUndant Pipeline Structures for Yield and Yield/Area Improvement.

Mohammad Mirza-Aghatabar, Melvin A. Breuer, Sandeep K. Gupta

Proceedings of the Eighteentgh Asian Test Symposium, 2009

2008

An Error Rate Based Test Methodology to Support Error-Tolerance.

Tong-Yu Hsieh, Kuen-Jong Lee, Melvin A. Breuer

IEEE Trans. Reliab., 2008

An Illustrated Methodology for Analysis of Error Tolerance.

Melvin A. Breuer, Haiyang (Henry) Zhu

IEEE Des. Test Comput., 2008

Clarifying the record on testability cost functions.

Melvin A. Breuer

IEEE Des. Test Comput., 2008

Basing Acceptable Error-Tolerant Performance on Significance-Based Error-rate (SBER).

Zhaoliang Pan, Melvin A. Breuer

Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

A Multi-valued Algebra for Capacitance Induced Crosstalk Delay Faults.

Arani Sinha, Sandeep K. Gupta, Melvin A. Breuer

Proceedings of the 17th IEEE Asian Test Symposium, 2008

2007

Estimating Error Rate in Defective Logic Using Signature Analysis.

Zhaoliang Pan, Melvin A. Breuer

IEEE Trans. Computers, 2007

Reduction of detected acceptable faults for yield improvement via error-tolerance.

Tong-Yu Hsieh, Kuen-Jong Lee, Melvin A. Breuer

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Improving Timing-Independent Testing of Crosstalk Using Realistic Assumptions on Delay Faults.

Shahdad Irajpour, Sandeep K. Gupta, Melvin A. Breuer

Proceedings of the 16th Asian Test Symposium, 2007

2006

An Error-Oriented Test Methodology to Improve Yield with Error-Tolerance.

Tong-Yu Hsieh, Kuen-Jong Lee, Melvin A. Breuer

Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

Error-Tolerance and Multi-Media.

Melvin A. Breuer, Haiyang (Henry) Zhu

Proceedings of the Second International Conference on Intelligent Information Hiding and Multimedia Signal Processing (IIH-MSP 2006), 2006

STAX: statistical crosstalk target set compaction.

Shahin Nazarian, Massoud Pedram, Sandeep K. Gupta, Melvin A. Breuer

Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, 2006

Diagnosis of delay faults due to resistive bridges, delay variations and defects.

Lei Wang, Sandeep K. Gupta, Melvin A. Breuer

Proceedings of the 15th Asian Test Symposium, 2006

Test Generation for Weak Resistive Bridges.

Shahdad Irajpour, Sandeep K. Gupta, Melvin A. Breuer

Proceedings of the 15th Asian Test Symposium, 2006

2005

A novel test methodology based on error-rate to support error-tolerance.

Kuen-Jong Lee, Tong-Yu Hsieh, Melvin A. Breuer

Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Multiple tests for each gate delay fault: higher coverage and lower test application cost.

Shahdad Irajpour, Sandeep K. Gupta, Melvin A. Breuer

Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Let's Think Analog.

Melvin A. Breuer

Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

Multi-media Applications and Imprecise Computation.

Melvin A. Breuer

Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005

2004

Defect and Error Tolerance in the Presence of Massive Numbers of Defects.

Melvin A. Breuer, Sandeep K. Gupta, T. M. Mak

IEEE Des. Test Comput., 2004

Timing-Independent Testing of Crosstalk in the Presence of Delay Producing Defects Using Surrogate Fault Models.

Shahdad Irajpour, Sandeep K. Gupta, Melvin A. Breuer

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Determining error rate in error tolerant VLSI chips.

Melvin A. Breuer

Proceedings of the 2nd IEEE International Workshop on Electronic Design, 2004

Modeling and Simulation for Crosstalk Aggravated by Weak-Bridge Defects between On-Chip Interconnects.

Lei Wang, Sandeep K. Gupta, Melvin A. Breuer

Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

Efficient Identification of Crosstalk Induced Slowdown Targets.

Melvin A. Breuer, Sandeep K. Gupta, Shahin Nazarian

Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

Intelligible Test Techniques to Support Error-Tolerance.

Melvin A. Breuer

Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

2003

Analyzing Crosstalk in the Presence of Weak Bridge Defects.

Shahdad Irajpour, Shahin Nazarian, Lei Wang, Sandeep K. Gupta, Melvin A. Breuer

Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

Test Generation for Maximizing Ground Bounce Considering Circuit Delay.

Yi-Shing Chang, Sandeep K. Gupta, Melvin A. Breuer

Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

An Enhanced Test Generator for Capacitance Induced Crosstalk Delay Faults.

Arani Sinha, Sandeep K. Gupta, Melvin A. Breuer

Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

2002

Analytical models for crosstalk excitation and propagation in VLSI circuits.

Wei-Yu Chen, Sandeep K. Gupta, Melvin A. Breuer

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

TA-PSV - Timing Analysis for Partially Specified Vectors.

Liang-Chi Chen, Sandeep K. Gupta, Melvin A. Breuer

J. Electron. Test., 2002

Test Generation for Crosstalk-Induced Faults: Framework and Computational Results.

Wei-Yu Chen, Sandeep K. Gupta, Melvin A. Breuer

J. Electron. Test., 2002

XIDEN: Crosstalk Target Identification Framework.

Shahin Nazarian, Hang Huang, Suriyaprakash Natarajan, Sandeep K. Gupta, Melvin A. Breuer

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Accurate and Efficient Static Timing Analysis with Crosstalk.

I-De Huang, Sandeep K. Gupta, Melvin A. Breuer

Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

2001

Introducing redundant computations in RTL data paths for reducing BIST resources.

Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer

ACM Trans. Design Autom. Electr. Syst., 2001

Test Generation for Maximizing Ground Bounce for Internal Circuitry with Reconvergent Fan-out.

Yi-Shing Chang, Sandeep K. Gupta, Melvin A. Breuer

Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

Switch-level delay test of domino logic circuits.

Suriyaprakash Natarajan, Sandeep K. Gupta, Melvin A. Breuer

Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

Crosstalk test generation on pseudo industrial circuits: a case study.

Liang-Chi Chen, T. M. Mak, Sandeep K. Gupta, Melvin A. Breuer

Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

A New Gate Delay Model for Simultaneous Switching and Its Applications.

Liang-Chi Chen, Sandeep K. Gupta, Melvin A. Breuer

Proceedings of the 38th Design Automation Conference, 2001

2000

Fundamental CAD algorithms.

Melvin A. Breuer, Majid Sarrafzadeh, Fabio Somenzi

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Novel Test Pattern Generators for Pseudoexhaustive Testing.

Rajagopalan Srinivasan, Sandeep K. Gupta, Melvin A. Breuer

IEEE Trans. Computers, 2000

High End and Low End Applications for Defective Chips: Enhanced Availability and Acceptability.

Melvin A. Breuer

Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

New Validation and Test Problems for High Performance Deep Submicron VLSI Circuits.

Melvin A. Breuer, Sandeep K. Gupta

Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

Test generation for crosstalk-induced faults: framework and computational result.

Wei-Yu Chen, Sandeep K. Gupta, Melvin A. Breuer

Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

A new framework for static timing analysis, incremental timing refinement, and timing simulation.

Liang-Chi Chen, Sandeep K. Gupta, Melvin A. Breuer

Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

Challenges for the Academic Test Community.

Melvin A. Breuer, Kwang-Ting Cheng

Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

1999

Test Generation for Ground Bounce in Internal Logic Circuitry.

Yi-Shing Chang, Sandeep K. Gupta, Melvin A. Breuer

Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

Switch-level delay test.

Suriyaprakash Natarajan, Sandeep K. Gupta, Melvin A. Breuer

Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

Test generation for crosstalk-induced delay in integrated circuits.

Wei-Yu Chen, Sandeep K. Gupta, Melvin A. Breuer

Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

Validation and test generation for oscillatory noise in VLSI interconnects.

Arani Sinha, Sandeep K. Gupta, Melvin A. Breuer

Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

1998

Bounds on pseudoexhaustive test lengths.

Rajagopalan Srinivasan, Sandeep K. Gupta, Melvin A. Breuer

IEEE Trans. Very Large Scale Integr. Syst., 1998

Estimation of BIST Resources During High-Level Synthesis.

Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer

J. Electron. Test., 1998

Allocation Techniques for Reducing BIST Area Overhead of Data Paths.

Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer

J. Electron. Test., 1998

An IEEE 1149.1 Compliant Test Control Architecture.

Debaditya Mukherjee, Melvin A. Breuer

J. Electron. Test., 1998

Test generation in VLSI circuits for crosstalk noise.

Weiyu Chen, Sandeep K. Gupta, Melvin A. Breuer

Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

Process Variations and their Impact on Circuit Operation.

Suriyaprakash Natarajan, Melvin A. Breuer, Sandeep K. Gupta

Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 1998

Scheduling and Module Assignment for Reducing Bist Resources.

Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer

Proceedings of the 1998 Design, 1998

Introducing Redundant Computations in a Behavior for Reducing BIST Resources.

Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer

Proceedings of the 35th Conference on Design Automation, 1998

1997

High Quality Robust Tests for Path Delay Faults.

Liang-Chi Chen, Sandeep K. Gupta, Melvin A. Breuer

Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

Analysis of Ground Bounce in Deep Sub-Micron Circuits.

Yi-Shing Chang, Sandeep K. Gupta, Melvin A. Breuer

Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

Will 0.1um Digital Circuits Require Mixed-Signal Testing.

Melvin A. Breuer, Bozena Kaminska, John E. McDermid, V. Rayapathi, Donald L. Wheater

Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

Analytic Models for Crosstalk Delay and Pulse Analysis Under Non-Ideal Inputs.

Weiyu Chen, Melvin A. Breuer, Sandeep K. Gupta

Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

1996

Process-Aggravated Noise (PAN): New Validation and Test Problems.

Melvin A. Breuer, Sandeep K. Gupta

Proceedings of the Proceedings IEEE International Test Conference 1996, 1996

Lower Bounds on Test Resources for Scheduled Data Flow Graphs.

Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer

Proceedings of the 33st Conference on Design Automation, 1996

1995

Reconfiguration techniques for a single scan chain.

Sridhar Narayanan, Melvin A. Breuer

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Test embedding with discrete logarithms.

Mody Lempel, Sandeep K. Gupta, Melvin A. Breuer

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

An integrated system for assigning signal flow directions to CMOS transistors.

Kuen-Jong Lee, Chih-Nan Wang, Rajiv Gupta, Melvin A. Breuer

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Partial scan design of register-transfer level circuits.

Rajesh Gupta, Melvin A. Breuer

J. Electron. Test., 1995

Asynchronous multiple scan chain.

Sridhar Narayanan, Melvin A. Breuer

Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995

Data Path Allocation for Synthesizing RTL Designs with Low BIST Area Overhead.

Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer

Proceedings of the 32st Conference on Design Automation, 1995

1994

SWiTEST: a switch level test generation system for CMOS combinational circuits.

Kuen-Jong Lee, Charles Njinda, Melvin A. Breuer

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

Control Strategies for Chip-Based DFT/BIST Hardware.

Debaditya Mukherjee, Massoud Pedram, Melvin A. Breuer

Proceedings of the Proceedings IEEE International Test Conference 1994, 1994

A Low Cost BIST Methodology and Associated Novel Test Pattern Generator.

Sen-Pin Lin, Sandeep K. Gupta, Melvin A. Breuer

Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

Extraction of a High-level structural Representation from Circuit Descriptions with Applications to DFT/BIST.

Ishwar Parulkar, Melvin A. Breuer, Charles Njinda

Proceedings of the 31st Conference on Design Automation, 1994

1993

Optimal Configuring of Multiple Scan Chains.

Sridhar Narayanan, Rajesh Gupta, Melvin A. Breuer

IEEE Trans. Computers, 1993

Generating a family of testable designs using the BILBO methodology.

Sen-Pin Lin, Charles Njinda, Melvin A. Breuer

J. Electron. Test., 1993

Test program synthesis for modules and chips having boundary scan.

Jung-Cheun Lien, Melvin A. Breuer

J. Electron. Test., 1993

Novel Test Pattern Generators for Pseudo-Exhaustive Testing.

Rajagopalan Srinivasan, Sandeep K. Gupta, Melvin A. Breuer

Proceedings of the Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics, 1993

Reconfigurable scan chains: a novel approach to reduce test application time.

Sridhar Narayanan, Melvin A. Breuer

Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

Merging multiple FSM controllers for DFT/BIST hardware.

Debaditya Mukherjee, Massoud Pedram, Melvin A. Breuer

Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

An Efficient Partitioning Strategy for Pseudo-Exhaustive Testing.

Rajagopalan Srinivasan, Sandeep K. Gupta, Melvin A. Breuer

Proceedings of the 30th Design Automation Conference. Dallas, 1993

1992

Design and test rules for CMOS circuits to facilitate IDDQ testing of bridging faults.

Kuen-Jong Lee, Melvin A. Breuer

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

Testability properties of acyclic structures and applications to partial scan design.

Rajesh Gupta, Melvin A. Breuer

Proceedings of the 10th IEEE VLSI Test Symposium (VTS'92), 1992

Optimal Sequencing of Scan Registers.

Sridhar Narayanan, Charles Njinda, Melvin A. Breuer

Proceedings of the Proceedings IEEE International Test Conference 1992, 1992

Configuring multiple scan chains for minimum test time.

Sridhar Narayanan, Rajesh Gupta, Melvin A. Breuer

Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

SIESTA: a multi-facet scan design system.

Sridhar Narayanan, Charles Njinda, Rajesh Gupta, Melvin A. Breuer

Proceedings of the conference on European design automation, 1992

Minimal area merger of finite state machine controllers.

Debaditya Mukherjee, Massoud Pedram, Melvin A. Breuer

Proceedings of the conference on European design automation, 1992

1991

An optimal scheduling algorithm for testing interconnect using boundary scan.

Jung-Cheun Lien, Melvin A. Breuer

J. Electron. Test., 1991

The probability of error detection in sequential circuits using random test vectors.

Asad A. Ismaeel, Melvin A. Breuer

J. Electron. Test., 1991

Reorganizing Circuits to Aid Testability.

Rajiv Gupta, Rajagopalan Srinivasan, Melvin A. Breuer

IEEE Des. Test Comput., 1991

A partitioning method for achieving maximal test concurrency in pseudo-exhaustive testing.

Rajagopalan Srinivasan, Charles Njinda, Melvin A. Breuer

Proceedings of the 9th IEEE VLSI Test Symposium (VTS'91), 1991

Constraints for using IDDQ testing to detect CMOS bridging faults.

Kuen-Jong Lee, Melvin A. Breuer

Proceedings of the 9th IEEE VLSI Test Symposium (VTS'91), 1991

Maximal Diagnosis for Wiring Networks.

Jung-Cheun Lien, Melvin A. Breuer

Proceedings of the Proceedings IEEE International Test Conference 1991, 1991

Synthesis of Optimal 1-Hot Coded On-Chip Controllers for BIST Hardware.

Debaditya Mukherjee, Charles Njinda, Melvin A. Breuer

Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

A Systematic Approach for Designing Testable VLSI Circuits.

Sen-Pin Lin, Charles Njinda, Melvin A. Breuer

Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

Ordering Storage Elements in a Single Scan Chain.

Rajesh Gupta, Melvin A. Breuer

Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

1990

Fault Tolerance in Linear Systolic Arrays Using Time Redundancy.

Amitava Majumdar, Cauligi S. Raghavendra, Melvin A. Breuer

IEEE Trans. Computers, 1990

The BALLAST Methodology for Structured Partial Scan Design.

Rajesh Gupta, Rajiv Gupta, Melvin A. Breuer

IEEE Trans. Computers, 1990

On the charge sharing problem in CMOS stuck-open fault testing.

Kuen-Jong Lee, Melvin A. Breuer

Proceedings of the Proceedings IEEE International Test Conference 1990, 1990

Obstacles and an approach towards concurrent engineering.

Melvin A. Breuer

Proceedings of the Proceedings IEEE International Test Conference 1990, 1990

An Extensible User Interface for an Object-Oriented VLSI CAD Framework.

Rajiv Gupta, Melvin A. Breuer

Proceedings of the First International Conference on Systems Integration, 1990

A New Method for Assigning Signal Flow Directions to MOS Transistors.

Kuen-Jong Lee, Rajiv Gupta, Melvin A. Breuer

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

Digital systems testing and testable design.

Miron Abramovici, Melvin A. Breuer, Arthur D. Friedman

Computer Science Press, ISBN: 978-0-7167-8179-0, 1990

1989

Optimal routing of two rectangular blocks.

Mandalagiri S. Chandrasekhar, Melvin A. Breuer

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989

An Object-Oriented VLSI CAD Framework: A Case Study in Rapid Prototyping.

Rajiv Gupta, Wesley H. Cheng, Rajesh Gupta, Ido Hardonag, Melvin A. Breuer

Computer, 1989

BALLAST: a methodology for partial scan design.

Rajesh Gupta, Rajiv Gupta, Melvin A. Breuer

Proceedings of the Nineteenth International Symposium on Fault-Tolerant Computing, 1989

1988

Detectability of CMOS stuck-open faults using random and pseudorandom test sequences.

Sarma Sastry, Melvin A. Breuer

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988

Optimum design of IC power/ground nets subject to reliability constraints.

Salim U. Chowdhury, Melvin A. Breuer

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988

A knowledge-based system for selecting test methodologies.

Xi-an Zhu, Melvin A. Breuer

IEEE Des. Test, 1988

Analysis of testable PLA designs.

Xi-an Zhu, Melvin A. Breuer

IEEE Des. Test, 1988

Concurrent Control of Multiple BIT Structures.

Sandeep K. Gupta, Melvin A. Breuer, Jung-Cheun Lien

Proceedings of the Proceedings International Test Conference 1988, 1988

A Test and Maintenance Controller for a Module Containing Testable Chips.

Melvin A. Breuer, Jung-Cheun Lien

Proceedings of the Proceedings International Test Conference 1988, 1988

The POTATO chip architecture: a study in tradeoffs for signal processing chip design.

B. Sharma, Rajiv Jain, Melvin A. Breuer, Alice C. Parker, Cauligi S. Raghavendra, C. Y. Tseng

Proceedings of the Computer Design: VLSI in Computers and Processors, 1988

Fault tolerance and testing aspects of an architecture for a generalized sidelobe cancellor.

Melvin A. Breuer, Amitava Majumdar, Cauligi S. Raghavendra

Proceedings of the Computer Design: VLSI in Computers and Processors, 1988

Cbase 1.0: a CAD database for VLSI circuits using object oriented technology.

Melvin A. Breuer, Wesley H. Cheng, Rajiv Gupta, Ido Hardonag, Ellis Horowitz, S. Y. Lin

Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988

1987

Built-in test for folded programmable logic arrays.

Melvin A. Breuer, F. Saheban

Microprocess. Microsystems, 1987

1986

Roving Emulation as a Fault Detection Mechanism.

Melvin A. Breuer, Asad A. Ismaeel

IEEE Trans. Computers, 1986

Test Schedules for VLSI Circuits Having Built-In Test Hardware.

Magdy S. Abadir, Melvin A. Breuer

IEEE Trans. Computers, 1986

An O(n) algorithm for width determination of power/ground routes for VLSI circuits.

Salim U. Chowdhury, Melvin A. Breuer

Integr., 1986

Scan Path with Look Ahead Shifting (SPLASH).

Magdy S. Abadir, Melvin A. Breuer

Proceedings of the Proceedings International Test Conference 1986, 1986

A Knowledge-Based TDM Selection System.

Xi-an Zhu, Melvin A. Breuer

Proceedings of the Fall Joint Computer Conference, November 2-6, 1986, Dallas, Texas, USA, 1986

1985

Automatic Design for Testability Via Testability Measures.

Ting-Hua Chen, Melvin A. Breuer

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1985

A Knowledge-Based System for Designing Testable VLSI Chips.

Magdy S. Abadir, Melvin A. Breuer

IEEE Des. Test, 1985

The construction of minimal area power and ground nets for VLSI circuits.

Salim U. Chowdhury, Melvin A. Breuer

Proceedings of the 22nd ACM/IEEE conference on Design automation, 1985

A knowledge based system for selecting a test methodology for a PLA.

Melvin A. Breuer, Xi-an Zhu

Proceedings of the 22nd ACM/IEEE conference on Design automation, 1985

1984

On Area and Yield Considerations for Fault-Tolerant VLSI Processor Arrays.

Israel Koren, Melvin A. Breuer

IEEE Trans. Computers, 1984

1983

A methodology for custom VLSI layout.

Melvin A. Breuer, Anshul Kumar

IEEE Trans. Syst. Man Cybern., 1983

Efficient Single-Layer Routing Along a Line of Points.

Harold W. Carter, Melvin A. Breuer

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1983

A module interchange placement machine.

Alexander Iosupovicz, Clarence King, Melvin A. Breuer

Proceedings of the 20th Design Automation Conference, 1983

A placement algorithm for array processors.

Dah-Juh Chyan, Melvin A. Breuer

Proceedings of the 20th Design Automation Conference, 1983

1982

Fault Diagnosis in Synchronous Sequential Circuits Based on an Effect-Cause Analysis.

Miron Abramovici, Melvin A. Breuer

IEEE Trans. Computers, 1982

On routing for custom integrated circuits.

Zahir A. Syed, Abbas El Gamal, Melvin A. Breuer

Proceedings of the 19th Design Automation Conference, 1982

Optimum placement of two rectangular blocks.

Mandalagiri S. Chandrasekhar, Melvin A. Breuer

Proceedings of the 19th Design Automation Conference, 1982

A survey of the state-of-the-art of design automation an invited presentation.

Melvin A. Breuer

Proceedings of the 19th Design Automation Conference, 1982

1981

Probabilistic Aspects of Boolean Switching Functions via a New Transform.

Sarangan Krishna Kumar, Melvin A. Breuer

J. ACM, 1981

A Survey of the State of the Art of Design Automation.

Melvin A. Breuer, Arthur D. Friedman, Alexander Iosupovicz

Computer, 1981

Digital system simulation: Current status and future trends or darwin's theory of simulation.

Melvin A. Breuer, Alice C. Parker

Proceedings of the 18th Design Automation Conference, 1981

1980

Functional Level Primitives in Test Generation.

Melvin A. Breuer, Arthur D. Friedman

IEEE Trans. Computers, 1980

Multiple Fault Diagnosis in Combinational Circuits Based on an Effect-Cause Analysis.

Miron Abramovici, Melvin A. Breuer

IEEE Trans. Computers, 1980

A probabilistic model for the analysis of the routing process for circuits.

Prathima Agrawal, Melvin A. Breuer

Networks, 1980

Fault diagnosis based on effect-cause analysis: An introduction.

Miron Abramovici, Melvin A. Breuer

Proceedings of the 17th Design Automation Conference, 1980

1979

Experiments with a Density Router for PC Cards.

Prathima Agrawal, Melvin A. Breuer

IEEE Trans. Computers, 1979

On Redundancy and Fault Detection in Sequential Circuits.

Miron Abramovici, Melvin A. Breuer

IEEE Trans. Computers, 1979

Incremental processing applied to Steinberg's placement procedure.

Harold W. Carter, Melvin A. Breuer, Zahir A. Syed

Proceedings of the 16th Design Automation Conference, 1979

1978

Vector representation of switching and three-valued functions.

Ytzhak H. Levendel, Melvin A. Breuer

Proceedings of the eighth international symposium on Multiple-valued logic, 1978

Mathematical properties of Boolean transformations.

Ytzhak H. Levendel, Melvin A. Breuer

Proceedings of the eighth international symposium on Multiple-valued logic, 1978

1977

A class of min-cut placement algorithms.

Melvin A. Breuer

Proceedings of the 14th Design Automation Conference, 1977

Some theoretical aspects of algorithmic routing.

Prathima Agrawal, Melvin A. Breuer

Proceedings of the 14th Design Automation Conference, 1977

Concurrent fault simulation and functional level modeling.

Miron Abramovici, Melvin A. Breuer, K. Kumar

Proceedings of the 14th Design Automation Conference, 1977

The design of self-checking multi-output combinational circuits.

Danny C. C. Ko, Melvin A. Breuer

Proceedings of the American Federation of Information Processing Societies: 1977 National Computer Conference, 1977

1976

Identification of Multiple Stuck-Type Faults in Combinational Networks.

Melvin A. Breuer, Shih-Jeh Chang, Stephen Y. H. Su

IEEE Trans. Computers, 1976

1974

Procedures for Eliminating Static and Dynamic Hazards in Test Generation.

Melvin A. Breuer, R. Loyd Harrison

IEEE Trans. Computers, 1974

The Effects of Races, Delays, and Delay Faults on Test Generation.

Melvin A. Breuer

IEEE Trans. Computers, 1974

Initial design concepts for an advanced design automation system.

Melvin A. Breuer, Arthur D. Friedman

Proceedings of the 11th Design Automation Workshop, 1974

Curriculum on design automation at the University of Southern California.

Melvin A. Breuer

Proceedings of the 1974 ACM Annual Conference, 1974

1973

Testing for Intermittent Faults in Digital Circuits.

Melvin A. Breuer

IEEE Trans. Computers, 1973

1972

A Note on Three-Valued Logic Simulation.

Melvin A. Breuer

IEEE Trans. Computers, 1972

Generation of Fault Tests for Linear Logic Networks.

Melvin A. Breuer

IEEE Trans. Computers, 1972

Recent Developments in Design Automation.

Melvin A. Breuer

Computer, 1972

1971

A Random and an Algorithmic Technique for Fault Detection Test Generation for Sequential Circuits.

Melvin A. Breuer

IEEE Trans. Computers, 1971

1970

Functional Partitioning and Simulation of Digital Circuits.

Melvin A. Breuer

IEEE Trans. Computers, 1970

Simplification of the Covering Problem with Application to Boolean Expressions.

Melvin A. Breuer

J. ACM, 1970

1969

Combinatorial Equivalence of (0, 1) Circulant Matrices.

Melvin A. Breuer

J. Comput. Syst. Sci., 1969

Generation of optimal code for expressions via factorization.

Melvin A. Breuer

Commun. ACM, 1969

1968

Fault Detection in a Linear Cascade of Identical Machines

Melvin A. Breuer

Proceedings of the 9th Annual Symposium on Switching and Automata Theory, 1968

Hardware fault detection.

Melvin A. Breuer

Proceedings of the American Federation of Information Processing Societies: Proceedings of the AFIPS '68 Fall Joint Computer Conference, December 9-11, 1968, San Francisco, California, USA, 1968

Heuristic switching expression simplification.

Melvin A. Breuer

Proceedings of the 23rd ACM national conference, 1968

1967

Adaptive Computers

Melvin A. Breuer

Inf. Control., October, 1967

1966

Coding the vertexes of a graph.

Melvin A. Breuer

IEEE Trans. Inf. Theory, 1966

The application of integer programming in design automation.

Melvin A. Breuer

Proceedings of the SHARE design automation project, 1966

1965

Implementation of Threshold Nets by Integer Linear Programming.

Melvin A. Breuer

IEEE Trans. Electron. Comput., 1965

1964

Techniques for the simulation of computer logic.

Melvin A. Breuer

Commun. ACM, 1964

1962

Computer design: The minimization of Boolean functions containing unequal and nonlinear cost functions.

Melvin A. Breuer

Proceedings of the 1962 ACM national conference, Digest of technical papers, 1962