Melvin A. Breuer

Affiliations:
  • University of Southern California, Los Angeles, USA


According to our database1, Melvin A. Breuer authored at least 185 papers between 1962 and 2016.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of two.

Awards

IEEE Fellow

IEEE Fellow 1985, "For contributions in design automation and fault-tolerant computing.".

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2016
Testable MUTEX Design.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

2015
GlYFF: A framework for global yield and floorplan aware design optimization.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

Design and Analysis of Testable Mutual Exclusion Elements.
Proceedings of the 21st IEEE International Symposium on Asynchronous Circuits and Systems, 2015

Blade - A Timing Violation Resilient Asynchronous Template.
Proceedings of the 21st IEEE International Symposium on Asynchronous Circuits and Systems, 2015

Performance Optimization and Analysis of Blade Designs under Delay Variability.
Proceedings of the 21st IEEE International Symposium on Asynchronous Circuits and Systems, 2015

2013
Trading off area, yield and performance via hybrid redundancy in multi-core architectures.
Proceedings of the 31st IEEE VLSI Test Symposium, 2013

Using explicit output comparisons for fault tolerant scheduling (FTS) on modern high-performance processors.
Proceedings of the Design, Automation and Test in Europe, 2013

A new paradigm for trading off yield, area and performance to enhance performance per wafer.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
Error Rate Estimation for Defective Circuits via Ones Counting.
ACM Trans. Design Autom. Electr. Syst., 2012

Efficient Overdetection Elimination of Acceptable Faults for Yield Improvement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

A design flow to maximize yield/area of physical devices via redundancy.
Proceedings of the 2012 IEEE International Test Conference, 2012

Theory of redundancy for logic circuits to maximize yield/area.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

2011
An Error-Tolerance-Based Test Methodology to Support Product Grading for Yield Enhancement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

2010
Algorithms to maximize yield and enhance yield/area of pipeline circuitry by insertion of switches and redundant modules.
Proceedings of the Design, Automation and Test in Europe, 2010

Hardware that produces bounded rather than exact results.
Proceedings of the 47th Design Automation Conference, 2010

HYPER: A Heuristic for Yield/Area imProvEment Using Redundancy in SoC.
Proceedings of the 19th IEEE Asian Test Symposium, 2010

2009
Tolerance of performance degrading faults for effective yield improvement.
Proceedings of the 2009 IEEE International Test Conference, 2009

SIRUP: Switch Insertion in RedUndant Pipeline Structures for Yield and Yield/Area Improvement.
Proceedings of the Eighteentgh Asian Test Symposium, 2009

2008
An Error Rate Based Test Methodology to Support Error-Tolerance.
IEEE Trans. Reliab., 2008

An Illustrated Methodology for Analysis of Error Tolerance.
IEEE Des. Test Comput., 2008

Clarifying the record on testability cost functions.
IEEE Des. Test Comput., 2008

Basing Acceptable Error-Tolerant Performance on Significance-Based Error-rate (SBER).
Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

A Multi-valued Algebra for Capacitance Induced Crosstalk Delay Faults.
Proceedings of the 17th IEEE Asian Test Symposium, 2008

2007
Estimating Error Rate in Defective Logic Using Signature Analysis.
IEEE Trans. Computers, 2007

Reduction of detected acceptable faults for yield improvement via error-tolerance.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006
An Error-Oriented Test Methodology to Improve Yield with Error-Tolerance.
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

Error-Tolerance and Multi-Media.
Proceedings of the Second International Conference on Intelligent Information Hiding and Multimedia Signal Processing (IIH-MSP 2006), 2006

STAX: statistical crosstalk target set compaction.
Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, 2006

2005
A novel test methodology based on error-rate to support error-tolerance.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Multiple tests for each gate delay fault: higher coverage and lower test application cost.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Let's Think Analog.
Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

Multi-media Applications and Imprecise Computation.
Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005

2004
Defect and Error Tolerance in the Presence of Massive Numbers of Defects.
IEEE Des. Test Comput., 2004

Timing-Independent Testing of Crosstalk in the Presence of Delay Producing Defects Using Surrogate Fault Models.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Determining error rate in error tolerant VLSI chips.
Proceedings of the 2nd IEEE International Workshop on Electronic Design, 2004

Modeling and Simulation for Crosstalk Aggravated by Weak-Bridge Defects between On-Chip Interconnects.
Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

Efficient Identification of Crosstalk Induced Slowdown Targets.
Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

Intelligible Test Techniques to Support Error-Tolerance.
Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

2003
Analyzing Crosstalk in the Presence of Weak Bridge Defects.
Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

Test Generation for Maximizing Ground Bounce Considering Circuit Delay.
Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

An Enhanced Test Generator for Capacitance Induced Crosstalk Delay Faults.
Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

2002
Analytical models for crosstalk excitation and propagation in VLSI circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

TA-PSV - Timing Analysis for Partially Specified Vectors.
J. Electron. Test., 2002

Test Generation for Crosstalk-Induced Faults: Framework and Computational Results.
J. Electron. Test., 2002

XIDEN: Crosstalk Target Identification Framework.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Accurate and Efficient Static Timing Analysis with Crosstalk.
Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

2001
Introducing redundant computations in RTL data paths for reducing BIST resources.
ACM Trans. Design Autom. Electr. Syst., 2001

Test Generation for Maximizing Ground Bounce for Internal Circuitry with Reconvergent Fan-out.
Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

Switch-level delay test of domino logic circuits.
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

Crosstalk test generation on pseudo industrial circuits: a case study.
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

A New Gate Delay Model for Simultaneous Switching and Its Applications.
Proceedings of the 38th Design Automation Conference, 2001

2000
Fundamental CAD algorithms.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Novel Test Pattern Generators for Pseudoexhaustive Testing.
IEEE Trans. Computers, 2000

High End and Low End Applications for Defective Chips: Enhanced Availability and Acceptability.
Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

New Validation and Test Problems for High Performance Deep Submicron VLSI Circuits.
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

Test generation for crosstalk-induced faults: framework and computational result.
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

A new framework for static timing analysis, incremental timing refinement, and timing simulation.
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

Challenges for the Academic Test Community.
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

1999
Test Generation for Ground Bounce in Internal Logic Circuitry.
Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

Switch-level delay test.
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

Test generation for crosstalk-induced delay in integrated circuits.
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

Validation and test generation for oscillatory noise in VLSI interconnects.
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

1998
Bounds on pseudoexhaustive test lengths.
IEEE Trans. Very Large Scale Integr. Syst., 1998

Estimation of BIST Resources During High-Level Synthesis.
J. Electron. Test., 1998

Allocation Techniques for Reducing BIST Area Overhead of Data Paths.
J. Electron. Test., 1998

An IEEE 1149.1 Compliant Test Control Architecture.
J. Electron. Test., 1998

Test generation in VLSI circuits for crosstalk noise.
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

Process Variations and their Impact on Circuit Operation.
Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 1998

Scheduling and Module Assignment for Reducing Bist Resources.
Proceedings of the 1998 Design, 1998

Introducing Redundant Computations in a Behavior for Reducing BIST Resources.
Proceedings of the 35th Conference on Design Automation, 1998

1997
High Quality Robust Tests for Path Delay Faults.
Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

Analysis of Ground Bounce in Deep Sub-Micron Circuits.
Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

Will 0.1um Digital Circuits Require Mixed-Signal Testing.
Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

Analytic Models for Crosstalk Delay and Pulse Analysis Under Non-Ideal Inputs.
Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

1996
Process-Aggravated Noise (PAN): New Validation and Test Problems.
Proceedings of the Proceedings IEEE International Test Conference 1996, 1996

Lower Bounds on Test Resources for Scheduled Data Flow Graphs.
Proceedings of the 33st Conference on Design Automation, 1996

1995
Reconfiguration techniques for a single scan chain.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Test embedding with discrete logarithms.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

An integrated system for assigning signal flow directions to CMOS transistors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Partial scan design of register-transfer level circuits.
J. Electron. Test., 1995

Asynchronous multiple scan chain.
Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995

Data Path Allocation for Synthesizing RTL Designs with Low BIST Area Overhead.
Proceedings of the 32st Conference on Design Automation, 1995

1994
SWiTEST: a switch level test generation system for CMOS combinational circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

Control Strategies for Chip-Based DFT/BIST Hardware.
Proceedings of the Proceedings IEEE International Test Conference 1994, 1994

A Low Cost BIST Methodology and Associated Novel Test Pattern Generator.
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

Extraction of a High-level structural Representation from Circuit Descriptions with Applications to DFT/BIST.
Proceedings of the 31st Conference on Design Automation, 1994

1993
Optimal Configuring of Multiple Scan Chains.
IEEE Trans. Computers, 1993

Generating a family of testable designs using the BILBO methodology.
J. Electron. Test., 1993

Test program synthesis for modules and chips having boundary scan.
J. Electron. Test., 1993

Novel Test Pattern Generators for Pseudo-Exhaustive Testing.
Proceedings of the Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics, 1993

Reconfigurable scan chains: a novel approach to reduce test application time.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

Merging multiple FSM controllers for DFT/BIST hardware.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

An Efficient Partitioning Strategy for Pseudo-Exhaustive Testing.
Proceedings of the 30th Design Automation Conference. Dallas, 1993

1992
Design and test rules for CMOS circuits to facilitate IDDQ testing of bridging faults.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

Testability properties of acyclic structures and applications to partial scan design.
Proceedings of the 10th IEEE VLSI Test Symposium (VTS'92), 1992

Optimal Sequencing of Scan Registers.
Proceedings of the Proceedings IEEE International Test Conference 1992, 1992

Configuring multiple scan chains for minimum test time.
Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

SIESTA: a multi-facet scan design system.
Proceedings of the conference on European design automation, 1992

Minimal area merger of finite state machine controllers.
Proceedings of the conference on European design automation, 1992

1991
An optimal scheduling algorithm for testing interconnect using boundary scan.
J. Electron. Test., 1991

The probability of error detection in sequential circuits using random test vectors.
J. Electron. Test., 1991

Reorganizing Circuits to Aid Testability.
IEEE Des. Test Comput., 1991

A partitioning method for achieving maximal test concurrency in pseudo-exhaustive testing.
Proceedings of the 9th IEEE VLSI Test Symposium (VTS'91), 1991

Constraints for using IDDQ testing to detect CMOS bridging faults.
Proceedings of the 9th IEEE VLSI Test Symposium (VTS'91), 1991

Maximal Diagnosis for Wiring Networks.
Proceedings of the Proceedings IEEE International Test Conference 1991, 1991

Synthesis of Optimal 1-Hot Coded On-Chip Controllers for BIST Hardware.
Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

A Systematic Approach for Designing Testable VLSI Circuits.
Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

Ordering Storage Elements in a Single Scan Chain.
Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

1990
Fault Tolerance in Linear Systolic Arrays Using Time Redundancy.
IEEE Trans. Computers, 1990

The BALLAST Methodology for Structured Partial Scan Design.
IEEE Trans. Computers, 1990

On the charge sharing problem in CMOS stuck-open fault testing.
Proceedings of the Proceedings IEEE International Test Conference 1990, 1990

Obstacles and an approach towards concurrent engineering.
Proceedings of the Proceedings IEEE International Test Conference 1990, 1990

An Extensible User Interface for an Object-Oriented VLSI CAD Framework.
Proceedings of the First International Conference on Systems Integration, 1990

A New Method for Assigning Signal Flow Directions to MOS Transistors.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

Digital systems testing and testable design.
Computer Science Press, ISBN: 978-0-7167-8179-0, 1990

1989
Optimal routing of two rectangular blocks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989

An Object-Oriented VLSI CAD Framework: A Case Study in Rapid Prototyping.
Computer, 1989

BALLAST: a methodology for partial scan design.
Proceedings of the Nineteenth International Symposium on Fault-Tolerant Computing, 1989

1988
Detectability of CMOS stuck-open faults using random and pseudorandom test sequences.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988

Optimum design of IC power/ground nets subject to reliability constraints.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988

A knowledge-based system for selecting test methodologies.
IEEE Des. Test, 1988

Analysis of testable PLA designs.
IEEE Des. Test, 1988

Concurrent Control of Multiple BIT Structures.
Proceedings of the Proceedings International Test Conference 1988, 1988

A Test and Maintenance Controller for a Module Containing Testable Chips.
Proceedings of the Proceedings International Test Conference 1988, 1988

The POTATO chip architecture: a study in tradeoffs for signal processing chip design.
Proceedings of the Computer Design: VLSI in Computers and Processors, 1988

Fault tolerance and testing aspects of an architecture for a generalized sidelobe cancellor.
Proceedings of the Computer Design: VLSI in Computers and Processors, 1988

Cbase 1.0: a CAD database for VLSI circuits using object oriented technology.
Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988

1987
Built-in test for folded programmable logic arrays.
Microprocess. Microsystems, 1987

1986
Roving Emulation as a Fault Detection Mechanism.
IEEE Trans. Computers, 1986

Test Schedules for VLSI Circuits Having Built-In Test Hardware.
IEEE Trans. Computers, 1986

An O(n) algorithm for width determination of power/ground routes for VLSI circuits.
Integr., 1986

Scan Path with Look Ahead Shifting (SPLASH).
Proceedings of the Proceedings International Test Conference 1986, 1986

A Knowledge-Based TDM Selection System.
Proceedings of the Fall Joint Computer Conference, November 2-6, 1986, Dallas, Texas, USA, 1986

1985
Automatic Design for Testability Via Testability Measures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1985

A Knowledge-Based System for Designing Testable VLSI Chips.
IEEE Des. Test, 1985

The construction of minimal area power and ground nets for VLSI circuits.
Proceedings of the 22nd ACM/IEEE conference on Design automation, 1985

A knowledge based system for selecting a test methodology for a PLA.
Proceedings of the 22nd ACM/IEEE conference on Design automation, 1985

1984
On Area and Yield Considerations for Fault-Tolerant VLSI Processor Arrays.
IEEE Trans. Computers, 1984

1983
A methodology for custom VLSI layout.
IEEE Trans. Syst. Man Cybern., 1983

Efficient Single-Layer Routing Along a Line of Points.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1983

A module interchange placement machine.
Proceedings of the 20th Design Automation Conference, 1983

A placement algorithm for array processors.
Proceedings of the 20th Design Automation Conference, 1983

1982
Fault Diagnosis in Synchronous Sequential Circuits Based on an Effect-Cause Analysis.
IEEE Trans. Computers, 1982

On routing for custom integrated circuits.
Proceedings of the 19th Design Automation Conference, 1982

Optimum placement of two rectangular blocks.
Proceedings of the 19th Design Automation Conference, 1982

A survey of the state-of-the-art of design automation an invited presentation.
Proceedings of the 19th Design Automation Conference, 1982

1981
Probabilistic Aspects of Boolean Switching Functions via a New Transform.
J. ACM, 1981

A Survey of the State of the Art of Design Automation.
Computer, 1981

Digital system simulation: Current status and future trends or darwin's theory of simulation.
Proceedings of the 18th Design Automation Conference, 1981

1980
Functional Level Primitives in Test Generation.
IEEE Trans. Computers, 1980

Multiple Fault Diagnosis in Combinational Circuits Based on an Effect-Cause Analysis.
IEEE Trans. Computers, 1980

A probabilistic model for the analysis of the routing process for circuits.
Networks, 1980

Fault diagnosis based on effect-cause analysis: An introduction.
Proceedings of the 17th Design Automation Conference, 1980

1979
Experiments with a Density Router for PC Cards.
IEEE Trans. Computers, 1979

On Redundancy and Fault Detection in Sequential Circuits.
IEEE Trans. Computers, 1979

Incremental processing applied to Steinberg's placement procedure.
Proceedings of the 16th Design Automation Conference, 1979

1978
Vector representation of switching and three-valued functions.
Proceedings of the eighth international symposium on Multiple-valued logic, 1978

Mathematical properties of Boolean transformations.
Proceedings of the eighth international symposium on Multiple-valued logic, 1978

1977
A class of min-cut placement algorithms.
Proceedings of the 14th Design Automation Conference, 1977

Some theoretical aspects of algorithmic routing.
Proceedings of the 14th Design Automation Conference, 1977

Concurrent fault simulation and functional level modeling.
Proceedings of the 14th Design Automation Conference, 1977

The design of self-checking multi-output combinational circuits.
Proceedings of the American Federation of Information Processing Societies: 1977 National Computer Conference, 1977

1976
Identification of Multiple Stuck-Type Faults in Combinational Networks.
IEEE Trans. Computers, 1976

1974
Procedures for Eliminating Static and Dynamic Hazards in Test Generation.
IEEE Trans. Computers, 1974

The Effects of Races, Delays, and Delay Faults on Test Generation.
IEEE Trans. Computers, 1974

Initial design concepts for an advanced design automation system.
Proceedings of the 11th Design Automation Workshop, 1974

Curriculum on design automation at the University of Southern California.
Proceedings of the 1974 ACM Annual Conference, 1974

1973
Testing for Intermittent Faults in Digital Circuits.
IEEE Trans. Computers, 1973

1972
A Note on Three-Valued Logic Simulation.
IEEE Trans. Computers, 1972

Generation of Fault Tests for Linear Logic Networks.
IEEE Trans. Computers, 1972

Recent Developments in Design Automation.
Computer, 1972

1971
A Random and an Algorithmic Technique for Fault Detection Test Generation for Sequential Circuits.
IEEE Trans. Computers, 1971

1970
Functional Partitioning and Simulation of Digital Circuits.
IEEE Trans. Computers, 1970

Simplification of the Covering Problem with Application to Boolean Expressions.
J. ACM, 1970

1969
Combinatorial Equivalence of (0, 1) Circulant Matrices.
J. Comput. Syst. Sci., 1969

Generation of optimal code for expressions via factorization.
Commun. ACM, 1969

1968
Fault Detection in a Linear Cascade of Identical Machines
Proceedings of the 9th Annual Symposium on Switching and Automata Theory, 1968

Hardware fault detection.
Proceedings of the American Federation of Information Processing Societies: Proceedings of the AFIPS '68 Fall Joint Computer Conference, December 9-11, 1968, San Francisco, California, USA, 1968

Heuristic switching expression simplification.
Proceedings of the 23rd ACM national conference, 1968

1967
Adaptive Computers
Inf. Control., October, 1967

1966
Coding the vertexes of a graph.
IEEE Trans. Inf. Theory, 1966

The application of integer programming in design automation.
Proceedings of the SHARE design automation project, 1966

1965
Implementation of Threshold Nets by Integer Linear Programming.
IEEE Trans. Electron. Comput., 1965

1964
Techniques for the simulation of computer logic.
Commun. ACM, 1964

1962
Computer design: The minimization of Boolean functions containing unequal and nonlinear cost functions.
Proceedings of the 1962 ACM national conference, Digest of technical papers, 1962


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