Rajshekar Kalayappan
Orcid: 0000-0001-8154-2984
According to our database1,
Rajshekar Kalayappan
authored at least 15 papers
between 2013 and 2023.
Collaborative distances:
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Bibliography
2023
Proceedings of the 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems, 2023
2021
IEEE Trans. Dependable Secur. Comput., 2021
2020
ChunkedTejas: A Chunking-based Approach to Parallelizing a Trace-Driven Architectural Simulator.
ACM Trans. Model. Comput. Simul., 2020
2018
ACM Trans. Embed. Comput. Syst., 2018
2017
ACM Trans. Model. Comput. Simul., 2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
2016
FluidCheck: A Redundant Threading-Based Approach for Reliable Execution in Manycore Processors.
ACM Trans. Archit. Code Optim., 2016
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016
2015
Proceedings of the 25th International Workshop on Power and Timing Modeling, 2015
SecX: A Framework for Collecting Runtime Statistics for SoCs with Multiple Accelerators.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015
2014
Secur. Commun. Networks, 2014
2013