Ram Sivaramakrishnan

According to our database, Ram Sivaramakrishnan authored at least 4 papers between 2012 and 2015.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of three.

2015

M7: Oracle's Next-Generation Sparc Processor.

Kathirgamar Aingaran, Sumti Jairath, Georgios K. Konstadinidis, Serena Leung, Paul Loewenstein, Curtis McAllister, Stephen Phillips, Zoran Radovic, Ram Sivaramakrishnan, David Smentek, Thomas Wicki

IEEE Micro, 2015

2014

Next generation SPARC processor cache hierarchy.

Ram Sivaramakrishnan, Sumti Jairath

Proceedings of the 2014 IEEE Hot Chips 26 Symposium (HCS), 2014

2013

The Oracle Sparc T5 16-Core Processor Scales to Eight Sockets.

John R. Feehrer, Sumti Jairath, Paul Loewenstein, Ram Sivaramakrishnan, David Smentek, Sebastian Turullols, Ali Vahidsafa

IEEE Micro, 2013

2012

SPARC T5: 16-core CMT processor with glueless 1-hop scaling to 8-sockets.

Sebastian Turullols, Ram Sivaramakrishnan

Proceedings of the 2012 IEEE Hot Chips 24 Symposium (HCS), 2012