Sumti Jairath

According to our database, Sumti Jairath authored at least 9 papers between 2009 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2023

AI SoC Design Challenges in the Foundation Model Era.

Zhengyu Chen, Dawei Huang, Mingran Wang, Bowen Yang, Jinuk Luke Shin, Changran Hu, Bo Li, Raghu Prabhakar, Gao Deng, Yongning Sheng, Sihua Fu, Lu Yuan, Tian Zhao, Yun Du, Chen Liu, Jun Yang, Viren Shah, Venkat Srinivasan, Sumti Jairath

Proceedings of the IEEE Custom Integrated Circuits Conference, 2023

2022

SambaNova SN10 RDU: A 7nm Dataflow Architecture to Accelerate Software 2.0.

Raghu Prabhakar, Sumti Jairath, Jinuk Luke Shin

Proceedings of the IEEE International Solid-State Circuits Conference, 2022

2021

Accelerating Scientific Applications With SambaNova Reconfigurable Dataflow Architecture.

Murali Emani, Venkatram Vishwanath, Corey Adams, Michael E. Papka, Rick Stevens, Laura Florescu, Sumti Jairath, William Liu, Tejas Nama, Arvind Sujeeth, Volodymyr V. Kindratenko, Anne C. Elster

Comput. Sci. Eng., 2021

SambaNova SN10 RDU: Accelerating Software 2.0 with Dataflow.

Raghu Prabhakar, Sumti Jairath

Proceedings of the IEEE Hot Chips 33 Symposium, 2021

2016

Software in Silicon in the Oracle SPARC M7 processor.

Kathirgamar Aingaran, Sumti Jairath, David Lutz

Proceedings of the 2016 IEEE Hot Chips 28 Symposium (HCS), 2016

2015

M7: Oracle's Next-Generation Sparc Processor.

Kathirgamar Aingaran, Sumti Jairath, Georgios K. Konstadinidis, Serena Leung, Paul Loewenstein, Curtis McAllister, Stephen Phillips, Zoran Radovic, Ram Sivaramakrishnan, David Smentek, Thomas Wicki

IEEE Micro, 2015

2014

Next generation SPARC processor cache hierarchy.

Ram Sivaramakrishnan, Sumti Jairath

Proceedings of the 2014 IEEE Hot Chips 26 Symposium (HCS), 2014

2013

The Oracle Sparc T5 16-Core Processor Scales to Eight Sockets.

John R. Feehrer, Sumti Jairath, Paul Loewenstein, Ram Sivaramakrishnan, David Smentek, Sebastian Turullols, Ali Vahidsafa

IEEE Micro, 2013

2009

Simple Fairness Protocols for Daisy Chain Interconnects.

Wladek Olesinski, Hans Eberle, Nils Gura, Bob Dickson, Aron J. Silverton, Sumti Jairath, Peter Yakutis

Proceedings of the 17th IEEE Symposium on High Performance Interconnects, 2009