Ramesh Halli

According to our database, Ramesh Halli authored at least 5 papers between 2021 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2026

15.2 A 350mV Single-Rail SRAM Using a Custom-Logic-Bitcell in 2nm-CMOS-Nanosheet Technology for Mobile and Edge-AI Applications.

Manish Trivedi, Sandipan Sinha, Ramesh Halli, Girishankar Gurumurthy, Jaswinder Singh, Chun-Yuan Cheng, Linchien Chen, Jeff Lin, Hugh Mair

Proceedings of the IEEE International Solid-State Circuits Conference, 2026

2024

A 3nm Ultra High-Speed (4.5GHz) SRAM Cache Design With Wide DVFS Range.

Sandipan Sinha, Manish Trivedi, Jaswinder Singh, Sriharsha Enjapuri, Deepesh Gujjar, Ramesh Halli, Girishankar Gurumurthy

Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

2.1 A 4nm 3.4GHz Tri-Gear Fully Out-of-Order ARMv9.2 CPU Subsystem-Based 5G Mobile SoC.

Anshul Varma, Sumanth Gururajarao, HsinChen Chen, Tao Chen, Gordon Gammie, Hugh Mair, Jen-Hang Yang, Hao-Hsiang Yu, Shun-Chieh Chang, Cheng-Hao Yang, Li-An Huang, Kumar Ramanathan, Ramesh Halli, Efron Ho, Ta-Wen Hung, Sung S.-Y. Hsueh, LiangChe Li, Achuta Thippana, Ericbill Wang, Sa Hwang

Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2023

An Innovative Write Circuitry for Enhancing a 3nm L1 Cache Performance Across Wide DVFS Range.

Sandipan Sinha, Manish Trivedi, Jaswinder Singh, Sriharsha Enjapuri, Deepesh Gujjar, Ramesh Halli, Girishankar Gurumurthy

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2023

2021

A 5nm Wide Voltage Range Ultra High Density SRAM Design for L2/L3 Cache Applications.

Sriharsha Enjapuri, Deepesh Gujjar, Sandipan Sinha, Ramesh Halli, Manish Trivedi

Proceedings of the 34th International Conference on VLSI Design and 20th International Conference on Embedded Systems, 2021