Girishankar Gurumurthy

According to our database, Girishankar Gurumurthy authored at least 4 papers between 2017 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2026

15.2 A 350mV Single-Rail SRAM Using a Custom-Logic-Bitcell in 2nm-CMOS-Nanosheet Technology for Mobile and Edge-AI Applications.

Manish Trivedi, Sandipan Sinha, Ramesh Halli, Girishankar Gurumurthy, Jaswinder Singh, Chun-Yuan Cheng, Linchien Chen, Jeff Lin, Hugh Mair

Proceedings of the IEEE International Solid-State Circuits Conference, 2026

2024

A 3nm Ultra High-Speed (4.5GHz) SRAM Cache Design With Wide DVFS Range.

Sandipan Sinha, Manish Trivedi, Jaswinder Singh, Sriharsha Enjapuri, Deepesh Gujjar, Ramesh Halli, Girishankar Gurumurthy

Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

2023

An Innovative Write Circuitry for Enhancing a 3nm L1 Cache Performance Across Wide DVFS Range.

Sandipan Sinha, Manish Trivedi, Jaswinder Singh, Sriharsha Enjapuri, Deepesh Gujjar, Ramesh Halli, Girishankar Gurumurthy

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2023

2017

3.4 A 10nm FinFET 2.8GHz tri-gear deca-core CPU complex with optimized power-delivery network for mobile SoC performance.

Hugh Mair, Ericbill Wang, Alice Wang, Ping Kao, Yuwen Tsai, Sumanth Gururajarao, Rolf Lagerquist, Jin Son, Gordon Gammie, Gordon Lin, Achuta Thippana, Kent Li, Manzur Rahman, Wuan Kuo, David Yen, Yi-Chang Zhuang, Ue Fu, Hung-Wei Wang, Mark Peng, Cheng-Yuh Wu, Taner Dosluoglu, Anatoly Gelman, Daniel Dia, Girishankar Gurumurthy, Tony Hsieh, W. X. Lin, Ray Tzeng, Jengding Wu, C. H. Wang, Uming Ko

Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017