Remy Chevallier

According to our database1, Remy Chevallier authored at least 4 papers between 2005 and 2010.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2010
Formal Verification of Timed VHDL Programs.
Proceedings of the 2010 Forum on specification & Design Languages, 2010

2009
Timed verification of the generic architecture of a memory circuit using parametric timed automata.
Formal Methods Syst. Des., 2009

2006
Verification of the Generic Architecture of a Memory Circuit Using Parametric Timed Automata.
Proceedings of the Formal Modeling and Analysis of Timed Systems, 2006

2005
Verification of behavioral descriptions by combining symbolic simulation and automatic reasoning.
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005


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