Emmanuelle Encrenaz-Tiphène

According to our database1, Emmanuelle Encrenaz-Tiphène authored at least 39 papers between 1995 and 2018.

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Bibliography

2018
Modeling a Cache Coherence Protocol with the Guarded Action Language.
Proceedings of the Proceedings Third Workshop on Models for Formal Analysis of Real Systems and Sixth International Workshop on Verification and Program Transformation, 2018

2017
Symbolic Approach for Side-Channel Resistance Analysis of Masked Assembly Codes.
Proceedings of the PROOFS@CHES 2017, 2017

2015
Efficient Design and Evaluation of Countermeasures against Fault Attacks Using Formal Verification.
Proceedings of the Smart Card Research and Advanced Applications, 2015

2014
Formal verification of a software countermeasure against instruction skip attacks.
J. Cryptographic Engineering, 2014

Formal verification of a software countermeasure against instruction skip attacks.
CoRR, 2014

Experimental evaluation of two software countermeasures against fault attacks.
CoRR, 2014

Electromagnetic fault injection: towards a fault model on a 32-bit microcontroller.
CoRR, 2014

FSM-based properties and abstraction of components.
Proceedings of the 25nd IEEE International Symposium on Rapid System Prototyping, 2014

Mutation Based Feature Localization.
Proceedings of the 15th International Microprocessor Test and Verification Workshop, 2014

Experimental evaluation of two software countermeasures against fault attacks.
Proceedings of the 2014 IEEE International Symposium on Hardware-Oriented Security and Trust, 2014

2013
Formal verification of a software countermeasure against instruction skip attacks.
IACR Cryptology ePrint Archive, 2013

Electromagnetic Fault Injection: Towards a Fault Model on a 32-bit Microcontroller.
Proceedings of the 2013 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2013

Assisting refinement in System-on-Chip design.
Proceedings of the 2013 Forum on specification and Design Languages, 2013

Verification of heterogeneous systems: Theory and industrial experiences.
Proceedings of the 2013 Forum on specification and Design Languages, 2013

A Formally Verified Static Hypervisor with Hardware Support for a Many-Core Chip.
Proceedings of the Euro-Par 2013: Parallel Processing Workshops, 2013

2012
An efficient refinement strategy exploiting component properties in a cegar process.
Proceedings of the Proceeding of the 2012 Forum on Specification and Design Languages, 2012

2011
Feasibility analysis for robustness quantification by symbolic model checking.
Formal Methods in System Design, 2011

2010
Data decision diagrams for Promela systems analysis.
STTT, 2010

A Polynomial Algorithm to Prove Deadlock-Freeness of Wormhole Networks.
Proceedings of the 18th Euromicro Conference on Parallel, 2010

Formal Verification of Timed VHDL Programs.
Proceedings of the 2010 Forum on specification & Design Languages, 2010

2009
An Inverse Method for Parametric Timed Automata.
Int. J. Found. Comput. Sci., 2009

Timed verification of the generic architecture of a memory circuit using parametric timed automata.
Formal Methods in System Design, 2009

Automatic Verification of Counter Systems With Ranking Function.
Electr. Notes Theor. Comput. Sci., 2009

Complementary Formal Approaches for Dependability Analysis.
Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009

2008
A tool for automatic detection of deadlock in wormhole networks on chip.
ACM Trans. Design Autom. Electr. Syst., 2008

Time Separation of Events: An Inverse Method.
Electr. Notes Theor. Comput. Sci., 2008

An Inverse Method for Parametric Timed Automata.
Electr. Notes Theor. Comput. Sci., 2008

2007
CTL-property Transformations along an Incremental Design Process.
STTT, 2007

Using CTL formulae as component abstraction in a design and verification flow.
Proceedings of the Seventh International Conference on Application of Concurrency to System Design (ACSD 2007), 2007

2006
Formalizing the Incremental Design and Verification Process of a Pipelined Protocol Converter.
Proceedings of the 17th IEEE International Workshop on Rapid System Prototyping (RSP 2006), 2006

A Tool for Automatic Detection of Deadlock in Wormhole Networks on Chip.
Proceedings of the Eleventh Annual IEEE International High-Level Design Validation and Test Workshop 2006, 2006

Verification of the Generic Architecture of a Memory Circuit Using Parametric Timed Automata.
Proceedings of the Formal Modeling and Analysis of Timed Systems, 2006

2005
CTL-Property Transformations Along an Incremental Design Process.
Electr. Notes Theor. Comput. Sci., 2005

2003
CTL May Be Ambiguous When Model Checking Moore Machines.
Proceedings of the Correct Hardware Design and Verification Methods, 2003

Design Validation of ZCSP with SPIN.
Proceedings of the 3rd International Conference on Application of Concurrency to System Design (ACSD 2003), 2003

2002
Data Decision Diagrams for Petri Net Analysis.
Proceedings of the Applications and Theory of Petri Nets 2002, 2002

1998
Modular model checking of VLSI designs described in VHDL.
Proceedings of the Computers and Their Applications (CATA-98), 1998

1996
A Tool for Translation of VHDL Descriptions into a Formal Model and its Application to Formal Verification and Synthesis.
Proceedings of the Formal Techniques in Real-Time and Fault-Tolerant Systems, 1996

1995
A Symbolic Relation for a Subset of VHDL'87 Descriptions and its Application to Symbolic Model Checking.
Proceedings of the Correct Hardware Design and Verification Methods, 1995


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