Pirouz Bazargan-Sabet

According to our database1, Pirouz Bazargan-Sabet authored at least 15 papers between 1996 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2018
A 29 Gops/Watt 3D-Ready 16-Core Computing Fabric with Scalable Cache Coherent Architecture Using Distributed L2 and Adaptive L3 Caches.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018

2017
Smart security management in secure devices.
J. Cryptogr. Eng., 2017

2014
Power grid redundant path contribution in system on chip (SoC) robustness against electromigration.
Microelectron. Reliab., 2014

Power Noise Measurements of Cryptographic VLSI Circuits Regarding Side-Channel Information Leakage.
IEICE Trans. Electron., 2014

2013
Identifying signal correlations using discrete event simulation.
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013

2011
Implementation of Complex Strategies of Security Insecure Embedded Systems.
Proceedings of the 4th IFIP International Conference on New Technologies, 2011

2010
Formal Verification of Timed VHDL Programs.
Proceedings of the 2010 Forum on specification & Design Languages, 2010

2003
An Event-Driven Approach to Crosstalk Noise Analysis.
Proceedings of the Proceedings 36th Annual Simulation Symposium (ANSS-36 2003), Orlando, Florida, USA, March 30, 2003

2002
A MOS transistor model for peak voltage calculation of crosstalk noise.
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

2001
An Approach to Mapping the Timing Behavior of VLSI Circuits on Emulators.
Proceedings of the 12th IEEE International Workshop on Rapid System Prototyping (RSP 2001), 2001

A Model for Crosstalk Noise Evaluation in Deep Submicron Processes.
Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001

Modeling crosstalk noise for deep submicron verification tools.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

1998
Usinf Node Replication to improve Circuit's Partition in Distributed Logic Simulation.
Proceedings of the 12<sup>th</sup> European Simulation Multiconference - Simulation, 1998

Efficient Partitioning Method For Distributed Logic Simulation of VLSI Circuits.
Proceedings of the Proceedings 31st Annual Simulation Symposium (SS '98), 1998

1996
A symbolic simulation approach in resolving signals' correlation.
Proceedings of the Proceedings 29st Annual Simulation Symposium (SS '96), 1996


  Loading...