Renan Netto

According to our database1, Renan Netto authored at least 14 papers between 2013 and 2022.

Collaborative distances:

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2022
Algorithm Selection Framework for Legalization Using Deep Convolutional Neural Networks and Transfer Learning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

CR&P: An Efficient Co-operation between Routing and Placement.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021
ILP-Based Global Routing Optimization with Cell Movements.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021

2019
How Deep Learning Can Drive Physical Synthesis Towards More Predictable Legalization.
Proceedings of the 2019 International Symposium on Physical Design, 2019

2018
Enhancing Multi-Threaded Legalization Through k-d Tree Circuit Partitioning.
Proceedings of the 31st Symposium on Integrated Circuits and Systems Design, 2018

2017
Exploiting cache locality to speedup register clustering.
Proceedings of the 30th Symposium on Integrated Circuits and Systems Design: Chip on the Sands, 2017

How Game Engines Can Inspire EDA Tools Development: A use case for an open-source physical design library.
Proceedings of the 2017 ACM on International Symposium on Physical Design, 2017

2016
Clock-Tree-Aware Incremental Timing-Driven Placement.
ACM Trans. Design Autom. Electr. Syst., 2016

Evaluating the impact of circuit legalization on incremental optimization techniques.
Proceedings of the 29th Symposium on Integrated Circuits and Systems Design, 2016

Speeding up Incremental Legalization with Fast Queries to Multidimensional Trees.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Exploiting parallelism to speed up circuit legalization.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

2015
Timing-Driven Placement Based on Dynamic Net-Weighting for Efficient Slack Histogram Compression.
Proceedings of the 2015 Symposium on International Symposium on Physical Design, ISPD 2015, Monterey, CA, USA, March 29, 2015

Exploiting Non-Critical Steiner Tree Branches for Post-Placement Timing Optimization.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

2013
VLSI architectures for Digital Modulation Classification using Support Vector Machines.
Proceedings of the 4th IEEE Latin American Symposium on Circuits and Systems, 2013


  Loading...